Tobias Werner

According to our database, Tobias Werner authored at least 6 papers between 2013 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design-Technology Co-Optimizations for Power, Area, and Reliability.

Gerald Strevig, David Wolpert, Leon Sigal, Bill Huott, Mark Cichanowski, Noam Jungmann, Michael A. Sperling, Michael J. Becht, Matthias Pflanz, Daniel Kiss, Simon Büchsenstein, Tobias Werner, Philipp Salz, Michael Romain, Richard E. Serton, Nick Jing, Rajesh Veerabhadraiah, Dureseti Chidambarrao, Robert Arelt, Matt Angyal, Ben Trombley, Arvind Haran, Rahul M. Rao, Christopher J. Berry, Amanda Venton, Elazar Kachir, Andreas Arp

IEEE J. Solid State Circuits, January, 2026

2025

37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability.

David Wolpert, Gerry Strevig, Christopher J. Berry, Leon J. Sigal, Bill Huott, Mark Cichanowski, Matthias Pflanz, Tobias Werner, Philipp Salz, Nick Jinq, Michael Romain, Iris Leefken, Richard E. Serton, Rajesh Veerabhadraiah, Dureseti Chidambarrao, Robert Arelt, Matt Angyal, Ben Trombley, Arvind Haran, Stefan Hougardy, Ben Klotz, Rahul M. Rao

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2020

BonnCell: Automatic Cell Layout in the 7-nm Era.

Pascal Van Cleeff, Stefan Hougardy, Jannik Silvanus, Tobias Werner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018

IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors.

David Wolpert, Erwin Behnen, Leon J. Sigal, Yuen H. Chan, Gustavo Enrique Téllez, Douglas Bradley, Richard E. Serton, Rajesh Veerabhadraiah, William Ansley, Andrew Bianchi, Nagu Dhanwada, Sungjae Lee, Michael Scheuermann, Glen A. Wiedemeier, John Davis, Tobias Werner, Laura Darden, Keith G. Barkley, Michael Gray, Matthew Guzowski, Mitch DeHond, Timothy Schell, Stelios Tsapepas, Di Phan, Kriti Acharya, Jeffrey A. Zitz, Hunter F. Shi, Christopher J. Berry, James D. Warnock, Michael H. Wood, Robert M. Averill III

IBM J. Res. Dev., 2018

2015

4.1 22nm Next-generation IBM System z microprocessor.

James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.

John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013