Jérémy Postel-Pellerin

According to our database, Jérémy Postel-Pellerin authored at least 18 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability.

Hassen Aziza, Jérémy Postel-Pellerin, Hussein Bazzi, Mathieu Moreau, Adnan Harb

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Simulation of state of the art EEPROM programming window closure during endurance degradation.

Franck Matteo, Roberto Simola, Franck Melul, Karine Coulié, Jérémy Postel-Pellerin, Arnaud Régnier

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020

Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation.

Hussein Bazzi, Jérémy Postel-Pellerin, Hassen Aziza, Mathieu Moreau, Adnan Harb

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

True random number generation exploiting SET voltage variability in resistive RAM memory arrays.

Jérémy Postel-Pellerin, Hussein Bazzi, Hassen Aziza, Pierre Canet, Mathieu Moreau, Vincenzo Della Marca, Adnan Harb

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis.

Mounia Kharbouche-Harrari, Gregory di Pendina, Romain Wacquez, Bernard Dieny, Driss Aboulkassimi, Jérémy Postel-Pellerin, Jean-Michel Portal

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM.

Mounia Kharbouche-Harrari, Romain Wacquez, Gregory di Pendina, Jean-Max Dutertre, Jérémy Postel-Pellerin, Driss Aboulkassimi, Jean-Michel Portal

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits.

Hassen Aziza, Hussein Bazzi, Jérémy Postel-Pellerin, Pierre Canet, Mathieu Moreau, Adnan Harb

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2018

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction.

Vincenzo Della Marca, Jérémy Postel-Pellerin, Thibault Kempf, Arnaud Régnier, Philippe Chiquet, Marc Bocquet

Microelectron. Reliab., 2018

Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues.

Mounia Kharbouche-Harrari, Jérémy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

MRAM: from STT to SOT, for security and memory.

Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2016

Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories.

Pierre Canet, Jérémy Postel-Pellerin, Hassen Aziza

Microelectron. Reliab., 2016

2014

Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories.

Vincenzo Della Marca, Jérémy Postel-Pellerin, Guillaume Just, Pierre Canet, Jean-Luc Ogier

Microelectron. Reliab., 2014

2013

Access resistor modelling for EEPROM's retention test vehicle.

Pierre Canet, Jérémy Postel-Pellerin, Jean-Luc Ogier

Microelectron. Reliab., 2013

2012

Investigation of the effects of constant voltage stress on thin SiO₂ layers using dynamic measurement protocols.

Philippe Chiquet, Pascal Masson, Romain Laffont, Gilles Micolau, Jérémy Postel-Pellerin, Frédéric Lalande, Bernard Bouteille, Jean-Luc Ogier

Microelectron. Reliab., 2012

Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability.

Guillaume Just, Vincenzo Della Marca, Arnaud Régnier, Jean-Luc Ogier, Jérémy Postel-Pellerin, Jean-Michel Portal, Pascal Masson

J. Low Power Electron., 2012

2010

Leakage paths identification in NVM using biased data retention.

Jérémy Postel-Pellerin, Romain Laffont, Gilles Micolau, Frédéric Lalande, Arnaud Régnier, Bernard Bouteille

Microelectron. Reliab., 2010

2009

Modeling charge variation during data retention of MLC Flash memories.

Jérémy Postel-Pellerin, Frédéric Lalande, Pierre Canet, Rachid Bouchakour, F. Jeuland, L. Morancho

Microelectron. Reliab., 2009

Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories.

Jérémy Postel-Pellerin, Frédéric Lalande, Pierre Canet, Rachid Bouchakour, F. Jeuland, B. Bertello, B. Villard

Microelectron. Reliab., 2009