Wen Wang

Orcid: 0000-0002-3019-2336

Affiliations:
  • Yale University, Department of Electrical Engineering, New Haven, CT, USA


According to our database1, Wen Wang authored at least 22 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Universal Gaussian elimination hardware for cryptographic purposes.
J. Cryptogr. Eng., June, 2024

Towards a Polynomial Instruction Based Compiler for Fully Homomorphic Encryption Accelerators.
IACR Cryptol. ePrint Arch., 2024

GraSS: Graph-based Similarity Search on Encrypted Query.
IACR Cryptol. ePrint Arch., 2024

2023
Engineering Practical Rank-Code-Based Cryptographic Schemes on Embedded Hardware. A Case Study on ROLLO.
IEEE Trans. Computers, July, 2023

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

High-precision RNS-CKKS on fixed but smaller word-size architectures: theory and application.
Proceedings of the 11th Workshop on Encrypted Computing & Applied Homomorphic Cryptography, 2023

2022
An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Complete and Improved FPGA Implementation of Classic McEliece.
IACR Cryptol. ePrint Arch., 2022

2021
The Cost to Break SIKE: A Comparative Hardware-Based Analysis with AES and SHA-3.
Proceedings of the Advances in Cryptology - CRYPTO 2021, 2021

2020
Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA.
IACR Cryptol. ePrint Arch., 2020

ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography Algorithms.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
XMSS and Embedded Systems.
Proceedings of the Selected Areas in Cryptography - SAC 2019, 2019

Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V.
IACR Cryptol. ePrint Arch., 2018

FPGA-Based Niederreiter Cryptosystem Using Binary Goppa Codes.
Proceedings of the Post-Quantum Cryptography - 9th International Conference, 2018

Post-Quantum Cryptography on FPGAs: The Niederreiter Cryptosystem: Extended Abstract.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
FPGA-based Key Generator for the Niederreiter Cryptosystem Using Binary Goppa Codes.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017

2016
Solving large systems of linear equations over GF(2) on FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Design and implementation of open-source SATA III core for Stratix V FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016


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