Stéphane Donnay

According to our database1, Stéphane Donnay authored at least 59 papers between 1994 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2007
Scalable Gate-Level Models for Power and Timing Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
SWAN: high-level simulation methodology for digital substrate noise generation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Evolution of substrate noise generation mechanisms with CMOS technology scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Technologies for highly miniaturized autonomous sensor networks.
Microelectron. J., 2006

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate.
IEEE J. Solid State Circuits, 2006

A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Compensation of IQ imbalance and phase noise in OFDM systems.
IEEE Trans. Wirel. Commun., 2005

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates.
IEEE J. Solid State Circuits, 2005

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS.
IEEE J. Solid State Circuits, 2005

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors.
IEEE J. Solid State Circuits, 2005

Ultra wide-band body area channel model.
Proceedings of IEEE International Conference on Communications, 2005

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.
Proceedings of the 2005 Design, 2005

Substrate noise immune design of an LC-tank VCO using sensitivity functions.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
IEEE J. Solid State Circuits, 2004

Joint compensation of IQ imbalance, frequency offset and phase noise in OFDM receivers.
Eur. Trans. Telecommun., 2004

Compensation of transmitter IQ imbalance for OFDM systems.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Performance degradation of an LC-tank VCO by impact of digital switching noise.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Extended Subspace Identification of Improper Linear Systems.
Proceedings of the 2004 Design, 2004

Digital Ground Bounce Reduction by Phase Modulation of the Clock.
Proceedings of the 2004 Design, 2004

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
Proceedings of the 41th Design Automation Conference, 2004

A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
An analytic Volterra-series-based model for a MEMS variable capacitor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies.
IEEE J. Solid State Circuits, 2003

Single-carrier communication using decision-feedback equalization for multiple antennas.
Proceedings of IEEE International Conference on Communications, 2003

Compensation of IQ imbalance in OFDM systems.
Proceedings of IEEE International Conference on Communications, 2003

Joint compensation of IQ imbalance and frequency offset in OFDM systems.
Proceedings of the Global Telecommunications Conference, 2003

A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology.
Proceedings of the ESSCIRC 2003, 2003

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
Proceedings of the ESSCIRC 2003, 2003

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
Proceedings of the 2003 Design, 2003

Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits.
Proceedings of the 2003 Design, 2003

4G terminals: how are we going to design them?
Proceedings of the 40th Design Automation Conference, 2003

2002
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification.
IEEE J. Solid State Circuits, 2002

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits.
IEEE J. Solid State Circuits, 2002

High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions.
Proceedings of the 2002 Design, 2002

Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach .
Proceedings of the 2002 Design, 2002

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Proceedings of the 39th Design Automation Conference, 2002

2001
A Mixed-Signal Design Roadmap.
IEEE Des. Test Comput., 2001

OFDM versus Single Carrier with Cyclic Prefix: a system-based comparison.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

Efficient bit-error-rate estimation of multicarrier transceivers.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Chip-package codesign of a low-power 5-GHz RF front end.
Proc. IEEE, 2000

Analysis and experimental verification of digital substrate noise generation for epi-type substrates.
IEEE J. Solid State Circuits, 2000

Compact Modeling of Nonlinear Distortion in Analog Communication Circuits.
Proceedings of the 2000 Design, 2000

A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers.
Proceedings of the 37th Conference on Design Automation, 2000

High-level simulation of substrate noise generation including power supply noise coupling.
Proceedings of the 37th Conference on Design Automation, 2000

1999
High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

BANDIT: embedding analog-to-digital converters on digital telecom ASICs.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A Single-Package Solution for Wireless Transceivers.
Proceedings of the 1999 Design, 1999

1998
High-Level Power Minimization of Analog Sensor Interface Architectures.
Integr. Comput. Aided Eng., 1998

Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon.
Proceedings of the 1998 Design, 1998

1997
High-level synthesis of analog sensor interface front-ends.
Proceedings of the European Design and Test Conference, 1997

1995
A high-level design and optimization tool for analog RF receiver front-ends.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
A Methodology for Analog Design Automation in Mixed-Signal ASICs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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