Xiangyu Dong

ACM Trans. Archit. Code Optim., 2014

Preventing STT-RAM Last-Level Caches from Port Obstruction.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

Enabling high-performance LPDDRx-compatible MRAM.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

ProactiveDRAM: A DRAM-initiated retention management scheme.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies.

[BibT_eX]

[DOI]

Norman P. Jouppi

ACM Trans. Archit. Code Optim., 2013

A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies.

[BibT_eX]

[DOI]

Norman P. Jouppi

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Low-current probabilistic writes for power-efficient STT-RAM caches.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

i<sup>2</sup>WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

OAP: an obstruction-aware cache management policy for STT-RAM last-level caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Point and discard: a hard-error-tolerant architecture for non-volatile last level caches.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Influence of Stacked 3D Memory/Cache Architectures on GPUs.

[BibT_eX]

[DOI]

Narayanan Vijaykrishnan

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2011

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2011

Three-dimensional Integrated Circuits: Design, EDA, and Architecture.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2011

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.

[BibT_eX]

[DOI]

Narayanan Vijaykrishnan

Chita R. Das

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Energy-efficient multi-level cell phase-change memory system with data encoding.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

An energy-efficient 3D CMP design with fine-grained voltage scaling.

[BibT_eX]

[DOI]

Jishen Zhao

Proceedings of the Design, Automation and Test in Europe, 2011

Design implications of memristor-based RRAM cross-point structures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

AdaMS: Adaptive MLC/SLC phase-change memory design for file storage.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs.

[BibT_eX]

[DOI]

Jishen Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.

[BibT_eX]

[DOI]

Proceedings of the Conference on High Performance Computing Networking, 2010

Energy- and endurance-aware design of phase change memory caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Cost-aware three-dimensional (3D) many-core multiprocessor design.

[BibT_eX]

[DOI]

Jishen Zhao

Proceedings of the 47th Design Automation Conference, 2010

Cost-driven 3D integration with interconnect layers.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Energy and performance driven circuit design for emerging phase-change memory.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Architectural benefits and design challenges for three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

3D memory stacking for fast checkpointing/restore applications.

[BibT_eX]

[DOI]

Jing Xie

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM.

[BibT_eX]

[DOI]

Norman P. Jouppi

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A novel architecture of the 3D stacked MRAM L2 cache for CMPs.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).

[BibT_eX]

[DOI]