Adwait Jog

Orcid: 0000-0002-5525-7204

Affiliations:
  • University of Virginia, VA, USA
  • College of William and Mary, VA, USA (former)
  • Penn State, University Park, USA (former)


According to our database1, Adwait Jog authored at least 46 papers between 2012 and 2024.

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Bibliography

2024
Probing Weaknesses in GPU Reliability Assessment: A Cross-Layer Approach.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

2023
Asynchronous Automata Processing on GPUs.
Proc. ACM Meas. Anal. Comput. Syst., March, 2023

Path Forward Beyond Simulators: Fast and Accurate GPU Execution Time Prediction for DNN Workloads.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

A Regression-based Model for End-to-End Latency Prediction for DNN Execution on GPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Optimizing CPU Performance for Recommendation Systems At-Scale.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
Improving GPU Throughput through Parallel Execution Using Tensor Cores and CUDA Cores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
Practical Resilience Analysis of GPGPU Applications in the Presence of Single- and Multi-Bit Faults.
IEEE Trans. Computers, 2021

SUGAR: Speeding Up GPGPU Application Resilience Estimation with Input Sizing.
Proc. ACM Meas. Anal. Comput. Syst., 2021

Enabling Software Resilience in GPGPU Applications via Partial Thread Protection.
Proceedings of the 43rd IEEE/ACM International Conference on Software Engineering, 2021

Analyzing and Leveraging Decoupled L1 Caches in GPUs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Data-centric Reliability Management in GPUs.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

Accelerating DNN Architecture Search at Scale Using Selective Weight Transfer.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020
BCoal: Bucketing-Based Memory Coalescing for Efficient and Secure GPUs.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Characterizing Accuracy-Aware Resilience of GPGPU Applications.
Proceedings of the 20th IEEE/ACM International Symposium on Cluster, 2020

Why GPUs are Slow at Executing NFAs and How to Make them Faster.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

Analyzing and Leveraging Shared L1 Caches in GPUs.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Opportunistic computing in GPU architectures.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Address-stride assisted approximate load value prediction in GPUs.
Proceedings of the ACM International Conference on Supercomputing, 2019

Exploiting Latency and Error Tolerance of GPGPU Applications for an Energy-Efficient DRAM.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

Analyzing and Leveraging Remote-Core Bandwidth for Enhanced Performance in GPUs.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Quantifying Data Locality in Dynamic Parallelism in GPUs.
Proc. ACM Meas. Anal. Comput. Syst., 2018

Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance.
CoRR, 2018

Fault Site Pruning for Practical Reliability Analysis of GPGPU Applications.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Architectural Support for Efficient Large-Scale Automata Processing.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

RCoal: Mitigating GPU Timing Attack via Subwarp-Based Randomized Coalescing Techniques.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Improving Multi-Application Concurrency Support Within the GPU Memory System.
CoRR, 2017

Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Architecting SOT-RAM Based GPU Register File.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Controlled Kernel Launch for Dynamic Parallelism in GPUs.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps.
CoRR, 2016

Exploiting Core Criticality for Enhanced GPU Performance.
Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016

Zorua: A holistic approach to resource virtualization in GPUs.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Characterization of quantum workloads on SIMD architectures.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

μC-States: Fine-grained GPU Datapath Power Management.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Anatomy of GPU Memory System for Multi-Application Execution.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

A case for core-assisted bottleneck acceleration in GPUs: enabling flexible data compression with assist warps.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
Managing GPU Concurrency in Heterogeneous Architectures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications.
Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

Trading cache hit rate for memory performance.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Orchestrated scheduling and prefetching for GPGPUs.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

Neither more nor less: Optimizing thread-level parallelism for GPGPUs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012


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