Anton Tsertov

According to our database, Anton Tsertov authored at least 19 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Keynote: Cost-Efficient Reliability for Edge-AI Chips.

Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab

Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs.

Hardi Selg, Konstantin Shibin, Anton Tsertov, Maksim Jenihhin, Peeter Ellervee, Jaan Raik

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024

2023

On-Chip Sensors Data Collection and Analysis for SoC Health Management.

Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2019

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL.

Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov

Proceedings of the IEEE International Test Conference, 2019

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks.

Aleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov

Proceedings of the 24th IEEE European Test Symposium, 2019

2017

Automated software-based self-test generation for microprocessors.

Artjom Jasnetski, Raimund Ubar, Anton Tsertov

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

High-level test data generation for software-based self-test in microprocessors.

Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar

Proceedings of the 6th Mediterranean Conference on Embedded Computing, 2017

2016

On automatic software-based self-test program generation based on high-level decision diagrams.

Artjom Jasnetski, Raimund Ubar, Anton Tsertov

Proceedings of the 17th Latin-American Test Symposium, 2016

A suite of IEEE 1687 benchmark networks.

Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath

Proceedings of the 2016 IEEE International Test Conference, 2016

High-level modeling and testing of multiple control faults in digital systems.

Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

FPGA-controlled PCBA power-on self-test using processor's debug features.

Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams.

Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Software-based self-test generation for microprocessors with high-level decision diagrams.

Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik

Proceedings of the 15th Latin American Test Workshop, 2014

Laboratory framework TEAM for investigating the dependability issues of microprocessor systems.

Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013

On in-system programming of non-volatile memories.

Anton Tsertov, Sergei Devadze, Artur Jutman, Artjom Jasnetski

Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

2011

SoC and Board Modeling for Processor-Centric Board Testing.

Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models.

Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Testing beyond the SoCs in a lego style.

Anton Tsertov, Artur Jutman, Sergei Devadze

Proceedings of the 2010 East-West Design & Test Symposium, 2010

2008

Calculation of LFSR Seed and Polynomial Pair for BIST Applications.

Artur Jutman, Anton Tsertov, Raimund Ubar

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008