Bibiche M. Geuskens

According to our database1, Bibiche M. Geuskens authored at least 15 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
16.1 A nanogap transducer array on 32nm CMOS for electrochemical DNA sequencing.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2014

2013
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocess. Microsystems, 2013

2012
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.
IEEE J. Solid State Circuits, 2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.
IEEE J. Solid State Circuits, 2011

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

2010
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Resilient microprocessor design for high performance & energy efficiency.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Content Addressable Memory for Low-Power and High-Performance Applications.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009


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