Bruce F. Cockburn

IEEE Trans. Emerg. Top. Comput., 2022

2021

An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Fast and low-power leading-one detectors for energy-efficient logarithmic computing.

[BibT_eX]

[DOI]

Shyama Gandhi

IET Comput. Digit. Tech., 2021

A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks.

[BibT_eX]

[DOI]

Zijing Niu

Honglan Jiang

Leibo Liu

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis.

[BibT_eX]

[DOI]

Morgan Ledwon

IEEE Access, 2020

2019

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints.

[BibT_eX]

[DOI]

Honglan Jiang

Francisco J. H. Santiago

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression.

[BibT_eX]

[DOI]

Morgan Ledwon

Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

Approximate Leading One Detector Design for a Hardware-Efficient Mitchell Multiplier.

[BibT_eX]

[DOI]

Shyama Gandhi

Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2018

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Automatic Selection of Process Corner Simulations for Faster Design Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors.

[BibT_eX]

[DOI]

Honglan Jiang

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2017

Optimization of Low-Density Parity Check decoder performance for OpenCL designs synthesized to FPGAs.

[BibT_eX]

[DOI]

Andrew J. Maier

J. Parallel Distributed Comput., 2017

A true random number generator based on parallel STT-MTJs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Design, evaluation and fault-tolerance analysis of stochastic FIR filters.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

SRAM memory margin probability failure estimation using Gaussian Process regression.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Implementation of decoders for symmetric low density parity check codes on parallel computation platforms using OpenCL.

[BibT_eX]

[DOI]

Andrew J. Maier

Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

A novel gate grading approach for soft error tolerance in combinational circuits.

[BibT_eX]

[DOI]

Ali Mahani

Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015

Design and evaluation of stochastic FIR filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Pacific Rim Conference on Communications, 2015

Minimizing the number of process corner simulations during design verification.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Stochastic circuit design and performance evaluation of vector quantization.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

Electromagnetic Energy and Data Transfer for a Neural Implant.

[BibT_eX]

[DOI]

J. Ubiquitous Syst. Pervasive Networks, 2014

Neural Spike Compression Using Feature Extraction and a Fuzzy C-Means Codebook.

[BibT_eX]

[DOI]

Russell Dodd

Vincent C. Gaudet

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Adaptive dual-threshold neural signal compression suitable for implantable recording.

[BibT_eX]

[DOI]

Russell Dodd

Vincent C. Gaudet

Proceedings of the IEEE International Conference on Acoustics, 2014

Designing Next-generation Implantable Wireless Telemetry.

[BibT_eX]

[DOI]

Proceedings of the BIODEVICES 2014, 2014

2013

Electromagnetic Energy and Data Transfer in Biological Tissues Using Loop Antennas.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Ambient Systems, 2013

2012

Reconfigurable performance measurement system-on-a-chip for baseband wireless algorithm design and verification.

[BibT_eX]

[DOI]

IEEE Wirel. Commun., 2012

Hardware Implementation of Nakagami and Weibull Variate Generators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Layered space-time multiple-input multiple-output detector with parameterisable performance.

[BibT_eX]

[DOI]

Santosh V. Nagaraj

IET Commun., 2012

Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation.

[BibT_eX]

[DOI]

IET Commun., 2012

Low power asynchronous packet-based baseband transceiver for wireless sensor networks.

[BibT_eX]

[DOI]

Malihe Ahmadi

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011

Design and Characterization of a Multilevel DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Hardware Implementation of Rayleigh and Ricean Variate Generators.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models.

[BibT_eX]

[DOI]

IET Commun., 2011

Accurate multiple-input multiple-output fading channel simulator using a compact and highthroughput reconfigurable architecture.

[BibT_eX]

[DOI]

IET Commun., 2011

2010

An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2010

Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Near-optimal and efficient MIMO detectors for 64-QAM symbols.

[BibT_eX]

[DOI]

Arsene Pankeu Yomi

Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2009

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes.

[BibT_eX]

[DOI]

Tyler L. Brandon

John C. Koob

Leendert van den Berg

Zhengang Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Compact Rayleigh and Rician fading simulator based on random walk processes.

[BibT_eX]

[DOI]

IET Commun., 2009

High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A versatile fading simulator for on-chip verification of MIMO communication systems.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Single FPGA Filter-Based Multipath Fading Emulator.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

A flexible layered architecture for accurate digital baseband algorithm development and verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

FPGA-based accelerator for the verification of leading-edge wireless systems.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Modeling and Hardware Implementation Aspects of Fading Channel Simulators.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2008

A Compact and Accurate Gaussian Variate Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A Compact Single-FPGA Fading-Channel Simulator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A scalable LDPC decoder ASIC architecture with bit-serial message exchange.

[BibT_eX]

[DOI]

Siavash Sheikh Zeinoddin

Integr., 2008

An Accurate and Compact Rayleigh and Rician Fading Channel Simulator.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Hardware-based Error Rate Testing of Digital Baseband Communication Systems.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes.

[BibT_eX]

[DOI]

Tyler L. Brandon

John C. Koob

Leendert van den Berg

Zhengang Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A single-FPGA multipath MIMO fading channel simulator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the efficiency and accuracy of hybrid pseudo-random number generators for FPGA-based simulations.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2008

2007

Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Efficient allocation of packet-level forward error correction in video streaming over the Internet.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2007

An Improved SOS-Based Fading Channel Emulator.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE Vehicular Technology Conference, 2007

Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Flexible Filter Processor for Fading Channel Simulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2006

Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density.

[BibT_eX]

[DOI]

Tyler L. Brandon

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

On the Effects of Colored Noise on the Performance of LDPC Codes.

[BibT_eX]

[DOI]

Saeed Sharifi Tehrani

Stephen Bates

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A Reconfigurable SOS-based Rayleigh Fading Channel Simulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells.

[BibT_eX]

[DOI]

Keith Boyle

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005

Design of a 3-D fully depleted SOI computational RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Test and Characterization of a Variable-Capacity Multilevel DRAM.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

An investigation into three-level ferroelectric memory.

[BibT_eX]

[DOI]

Kamlesh R. Raiter

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2004

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms.

[BibT_eX]

[DOI]

Hongyu Liao

Mrinal Kr. Mandal

IEEE Trans. Signal Process., 2004

Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

2003

An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell.

[BibT_eX]

[DOI]

Daniel Salamon

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing.

[BibT_eX]

[DOI]

Jesús Hernández Tapia

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

The Emergence of High-Density Semiconductor-Compatible Spintronic Memory.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on MEMS, 2003

An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.

[BibT_eX]

[DOI]

Xiaoling Sun

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

An Investigation into Crosstalk Noise in DRAM Structures.

[BibT_eX]

[DOI]

Michael Redeker

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Panel on Advanced Embedded Memory Technologies.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001

Design of an Embedded Fully-Depleted SOI SRAM.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

1999

Voiceband signal classification using statistically optimal combinations of low-complexity discriminant variables.

[BibT_eX]

[DOI]

Jeremy S. Sewall

IEEE Trans. Commun., 1999

Fault Models and Tests for a 2-Bit-per-Cell MLDRAM.

[BibT_eX]

[DOI]

Michael Redeker

IEEE Des. Test Comput., 1999

Guest Editors' Introduction: DRAM Architecture and Testing.

[BibT_eX]

Fabrizio Lombardi

Fred J. Meyer

IEEE Des. Test Comput., 1999

A Comparative Simulation Study of Four Multilevel DRAMs.

[BibT_eX]

[DOI]

Gershom Birk

Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking.

[BibT_eX]

[DOI]

C. Wickman

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998

Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators.

[BibT_eX]

[DOI]

Albert L.-C. Kwong

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1995

Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs.

[BibT_eX]

[DOI]

Y.-F. Nicole Sat

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Tutorial on semiconductor memory testing.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

Deterministic tests for detecting single<i>V</i>-coupling faults in RAMs.

[BibT_eX]

[DOI]

J. Electron. Test., 1994

1992

Near-optimal tests for classes of write-triggered coupling faults in RAMs.

[BibT_eX]

[DOI]

Janusz A. Brzozowski

J. Electron. Test., 1992

1990

Switch-level testability of the dynamic CMOS PLA.

[BibT_eX]

[DOI]

Janusz A. Brzozowski

Integr., 1990

Detection of coupling faults in RAMs.

[BibT_eX]

[DOI]

Janusz A. Brzozowski