Claudio Rubattu

Orcid: 0000-0002-1265-4816

According to our database1, Claudio Rubattu authored at least 13 papers between 2016 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2021
PathTracer: Understanding Response Time of Signal Processing Applications on Heterogeneous MPSoCs.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design.
Microprocess. Microsystems, 2021

Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI.
CoRR, 2021

PathTracing: Raising the Level of Understanding of Processing Latency in Heterogeneous MPSoCs.
Proceedings of the DroneSE and RAPIDO '21: Methods and Tools, 2021

2020
Response time analysis of parameterized dataflow applications on heterogeneous SW/HW systems. (Analyse du temps de réponse des applications de flux de données paramétrées sur des systèmes logiciels/matériels hétérogènes).
PhD thesis, 2020

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA.
IEEE Access, 2020

2019
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
IEEE Embed. Syst. Lett., 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Extending Architecture Modeling for Signal Processing towards GPUs.
Proceedings of the 27th European Signal Processing Conference, 2019

A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

2017
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs.
J. Syst. Archit., 2017

Adaptive software-augmented hardware reconfiguration with dataflow design automation.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation.
Microprocess. Microsystems, 2016


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