Tiziana Fanni

Orcid: 0000-0002-4301-6497

According to our database1, Tiziana Fanni authored at least 30 papers between 2015 and 2022.

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Bibliography

2022
The Multi-Sensor Gateway, a Unified Communication Scheme and Orchestration Actor for Heterogeneous Systems.
Proceedings of the CPS Summer School PhD Workshop 2022 co-located with 4th Edition of the CPS Summer School (CPS 2022), 2022

Verification of Neural Networks: Challenges and Perspectives in the AIDOaRt Project (Short Paper).
Proceedings of the 10th Italian workshop on Planning and Scheduling (IPS 2022), RCRA Incontri E Confronti (RiCeRcA 2022), and the workshop on Strategies, Prediction, Interaction, and Reasoning in Italy (SPIRIT 2022) co-located with 21st International Conference of the Italian Association for Artificial Intelligence (AIxIA 2022), November 28, 2022

2021
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project.
Microprocess. Microsystems, November, 2021

A Composable Monitoring System for Heterogeneous Embedded Platforms.
ACM Trans. Embed. Comput. Syst., 2021

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design.
Microprocess. Microsystems, 2021

Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI.
CoRR, 2021

2020
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning.
ACM Trans. Design Autom. Electr. Syst., 2020

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA.
IEEE Access, 2020

Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Layering the monitoring action for improved flexibility and overhead control: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

2019
An integrated hardware/software design methodology for signal processing systems.
J. Syst. Archit., 2019

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding.
IEEE Access, 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Run-time performance monitoring of hardware accelerators: POSTER.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

DEMO: Multi-Grain Adaptivity in Cyber-Physical Systems.
Proceedings of the 30th International Conference on Microelectronics, 2018

2017
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy.
J. Signal Process. Syst., 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.
J. Syst. Archit., 2017

Challenging CPS Trade-off Adaptivity with Coarse-Grained Reconfiguration.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016
Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures.
J. Electr. Comput. Eng., 2016

Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Demo: Reconfigurable Platform Composer Tool.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Low power design methodology for signal processing systems using lightweight dataflow techniques.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Power and clock gating modelling in coarse grained reconfigurable systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Adaptable AES implementation with power-gating support.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Power modelling for saving strategies in coarse grained reconfigurable systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Automated power gating methodology for dataflow-based reconfigurable systems.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015


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