David Li

According to our database1, David Li authored at least 22 papers between 1994 and 2019.

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Timeline

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Bibliography

2019
Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs.
IEEE Trans. Industrial Electronics, 2019

Design Continuums and the Path Toward Self-Designing Key-Value Stores that Know and Learn.
Proceedings of the CIDR 2019, 2019

2018
Cross-Lingual Phoneme Mapping for Language Robust Contextual Speech Recognition.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Eigenface Algorithm-Based Facial Expression Recognition in Conversations - An Experimental Study.
Proceedings of the Advances in Brain Inspired Cognitive Systems, 2018

2017
Coordinated regulation of acid resistance in Escherichia coli.
BMC Systems Biology, 2017

A Survey of the State-of-the-Art Techniques for Cognitive Impairment Detection in the Elderly.
Proceedings of the Advanced Computational Methods in Life System Modeling and Simulation, 2017

Reduct: A Puzzle Game for Children About Evaluating Code.
Proceedings of the 2017 CHI Conference on Human Factors in Computing Systems, 2017

2015
Examples of challenges and opportunities in visual analysis in the digital humanities.
Proceedings of the Human Vision and Electronic Imaging XX, 2015

2013
Constant Delay Logic Style.
IEEE Trans. VLSI Syst., 2013

2012
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.
IEEE Trans. on Circuits and Systems, 2012

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator.
IEEE Trans. on Circuits and Systems, 2012

Created in China: the makings of China's hackerspace community.
Interactions, 2012

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Design and analysis of metastable-hardened flip-flops in sub-threshold region.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Comparative analysis and study of metastability on high-performance flip-flops.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2002
Constraint ordinal optimization.
Inf. Sci., 2002

2001

1997
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1994
Secure Short-Cut Routing for Mobile IP.
Proceedings of the USENIX Summer 1994 Technical Conference, 1994


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