Murali Jayapala

According to our database, Murali Jayapala authored at least 41 papers between 2001 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Intra-operative Brain Tumor Detection with Deep Learning-Optimized Hyperspectral Imaging.

Tommaso Giannantonio, Anna Alperovich, Piercosimo Semeraro, Manfredo Atzori, Xiaohan Zhang, Christoph Hauger, Alexander Freytag, Siri Luthman, Roeland Vandebriel, Murali Jayapala, Lien Solie, Steven De Vleeschouwer

CoRR, 2023

Drone-Based Corrosion Detection on High-Voltage Transmission Towers Using Hyperspectral Imaging.

Michiel Vlaminck, Zakaria Bnoulkacem, Gonzalo Luzardo, Hamed Zivariadab, Zohreh Zahiri, Bikram Koirala, Frédéric Mangialetto, Irid Bufi, Ljiljana Platisa, Murali Jayapala, Paul Scheunders, Hiêp Quang Luong

Proceedings of the 13th Workshop on Hyperspectral Imaging and Signal Processing: Evolution in Remote Sensing, 2023

Band Relevance Study of SWIR Hyperspectral Imaging for Material Recycling and Reuse.

Carolina Blanch Perez del Notario, Steven Thijs, Murali Jayapala

Proceedings of the 13th Workshop on Hyperspectral Imaging and Signal Processing: Evolution in Remote Sensing, 2023

2019

Graph and Rank Regularized Matrix Recovery for Snapshot Spectral Image Demosaicing.

Grigorios Tsagkatakis, Maarten Bloemen, Bert Geelen, Murali Jayapala, Panagiotis Tsakalides

IEEE Trans. Computational Imaging, 2019

2016

Non-negative Matrix Completion for the Enhancement of Snapshot Mosaic Multispectral Imagery.

Grigorios Tsagkatakis, Murali Jayapala, Bert Geelen, Panagiotis Tsakalides

Proceedings of the Image Sensors and Imaging Systems 2016, 2016

Characterization of VNIR Hyperspectral Sensors with Monolithically Integrated Optical Filters.

Prashant Agrawal, Klaas Tack, Bert Geelen, Bart Masschelein, Pablo Mateo Aranda Moran, Andy Lambrechts, Murali Jayapala

Proceedings of the Image Sensors and Imaging Systems 2016, 2016

2011

Automated architecture exploration for low energy reconfigurable AGU.

Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the International SoC Design Conference, 2011

2009

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.

Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest

IEEE Trans. Very Large Scale Integr. Syst., 2009

Playing the trade-off game: Architecture exploration using Coffeee.

Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor

ACM Trans. Design Autom. Electr. Syst., 2009

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.

Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest

IEEE Trans. Computers, 2009

EMPIRE: Empirical power/area/timing models for register files.

Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest

Microprocess. Microsystems, 2009

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.

Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Locality optimization in a compiler for wireless applications.

Javed Absar, Praveen Raghavan, Andy Lambrechts, Min Li, Murali Jayapala, Francky Catthoor

Des. Autom. Embed. Syst., 2009

Compilation Technique for Loop Overhead Minimization.

Nikolas Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Dimitrios Soudris

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.

Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Address Generation Optimization for Embedded High-Performance Processors: A Survey.

Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor

J. Signal Process. Syst., 2008

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.

Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Coffee: COmpiler Framework for Energy-Aware Exploration.

Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest

Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Operation shuffling over cycle boundaries for low energy L0 clustering.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

ACM Trans. Design Autom. Electr. Syst., 2007

Semi Custom Design: A Case Study on SIMD Shufflers.

Praveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.

Liesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Very wide register: an asymmetric register file organization for low power embedded processors.

Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest, Henk Corporaal

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Locality optimization in wireless applications.

Javed Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.

Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest

Proceedings of the Architecture of Computing Systems, 2007

2006

Instruction Transfer And Storage Exploration for Low Energy VLIWs.

Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.

Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.

Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck

IEEE Trans. Computers, 2005

Instruction buffering exploration for low energy embedded processors.

Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor

J. Embed. Comput., 2005

Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.

Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.

Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

L0 buffer energy optimization through scheduling and exploration.

Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Design Style Case Study for Embedded Multi Media Compute Nodes.

Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll

Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

L0 Cluster Synthesis and Operation Shuffling.

Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck

Proceedings of the Integrated Circuit and System Design, 2004

Instruction buffering exploration for low energy VLIWs with instruction clusters.

Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Low Power Coarse-Grained Reconfigurable Instruction Set Processor.

Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

Matador: An Exploration Environment for System-Design.

Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck

J. Circuits Syst. Comput., 2002

Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.

Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.

Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001

CRISP: A Template for Reconfigurable Instruction Set Processors.

Pieter Op de Beeck, Francisco Barat, Murali Jayapala, Rudy Lauwereins

Proceedings of the Field-Programmable Logic and Applications, 2001