Murali Jayapala

According to our database1, Murali Jayapala authored at least 36 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Graph and Rank Regularized Matrix Recovery for Snapshot Spectral Image Demosaicing.
IEEE Trans. Computational Imaging, 2019

Automated architecture exploration for low energy reconfigurable AGU.
Proceedings of the International SoC Design Conference, 2011

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
IEEE Trans. VLSI Syst., 2009

Playing the trade-off game: Architecture exploration using Coffeee.
ACM Trans. Design Autom. Electr. Syst., 2009

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.
IEEE Trans. Computers, 2009

EMPIRE: Empirical power/area/timing models for register files.
Microprocess. Microsystems, 2009

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.
IEICE Transactions, 2009

Locality optimization in a compiler for wireless applications.
Design Autom. for Emb. Sys., 2009

Compilation Technique for Loop Overhead Minimization.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Address Generation Optimization for Embedded High-Performance Processors: A Survey.
Signal Processing Systems, 2008

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.
IEICE Transactions, 2008

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Coffee: COmpiler Framework for Energy-Aware Exploration.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Operation shuffling over cycle boundaries for low energy L0 clustering.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
ACM Trans. Design Autom. Electr. Syst., 2007

Semi Custom Design: A Case Study on SIMD Shufflers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Very wide register: an asymmetric register file organization for low power embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Locality optimization in wireless applications.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.
Proceedings of the Architecture of Computing Systems, 2007

Instruction Transfer And Storage Exploration for Low Energy VLIWs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.
IEEE Trans. Computers, 2005

Instruction buffering exploration for low energy embedded processors.
J. Embedded Computing, 2005

Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

L0 buffer energy optimization through scheduling and exploration.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Design Style Case Study for Embedded Multi Media Compute Nodes.
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

L0 Cluster Synthesis and Operation Shuffling.
Proceedings of the Integrated Circuit and System Design, 2004

Instruction buffering exploration for low energy VLIWs with instruction clusters.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Low Power Coarse-Grained Reconfigurable Instruction Set Processor.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Matador: An Exploration Environment for System-Design.
Journal of Circuits, Systems, and Computers, 2002

Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

CRISP: A Template for Reconfigurable Instruction Set Processors.
Proceedings of the Field-Programmable Logic and Applications, 2001