David Turgis

According to our database1, David Turgis authored at least 12 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021

2018
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

2017
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2014

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell.
Proceedings of the International SoC Design Conference, 2012


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