Geraldo Pradipta

Orcid: 0000-0003-4599-6166

According to our database1, Geraldo Pradipta authored at least 8 papers between 2019 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes.
Proceedings of the 2025 International Symposium on Physical Design, 2025

GOALPlace: Begin with the End in Mind.
Proceedings of the 2025 International Symposium on Physical Design, 2025

2024
2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing Using ML Techniques and GPU Acceleration.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023
AutoDMP: Automated DREAMPlace-based Macro Placement.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
TransSizer: A Novel Transformer-Based Fast Gate Sizer.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Generative self-supervised learning for gate sizing: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2019
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019


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