Anthony Agnesina

Orcid: 0000-0003-0393-0230

According to our database1, Anthony Agnesina authored at least 23 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent.
CoRR, 2024

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation.
CoRR, 2024

Challenges for Automating PCB Layout.
Proceedings of the 2024 International Symposium on Physical Design, 2024

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner.
Proceedings of the 2024 International Symposium on Physical Design, 2024

GPU/ML-Enhanced Large Scale Global Routing Contest.
Proceedings of the 2024 International Symposium on Physical Design, 2024

2023
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers.
ACM Trans. Design Autom. Electr. Syst., September, 2023

Parameter Optimization of VLSI Placement Through Deep Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

On Legalization of Die Bonding Bumps and Pads for 3D ICs.
Proceedings of the 2023 International Symposium on Physical Design, 2023

AutoDMP: Automated DREAMPlace-based Macro Placement.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

2020
A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Improving FPGA-Based Logic Emulation Systems through Machine Learning.
ACM Trans. Design Autom. Electr. Syst., 2020

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM.
IEEE Comput. Archit. Lett., 2020

A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

VLSI Placement Parameter Optimization using Deep Reinforcement Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization.
Proceedings of the International Conference on Computer-Aided Design, 2019

Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
A novel 3D DRAM memory cube architecture for space applications.
Proceedings of the 55th Annual Design Automation Conference, 2018


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