Gert-Jan van Schaik

According to our database1, Gert-Jan van Schaik authored at least 13 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021

21.2 A 3-to-10GHz 180pJ/b IEEE802.15.4z/4a IR-UWB Coherent Polar Transmitter in 28nm CMOS with Asynchronous Amplitude Pulse-Shaping and Injection-Locked Phase Modulation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
30.6 A Low-Power BLE Transceiver with Support for Phase-Based Ranging, Featuring 5µs PLL Locking Time and 5.3ms Ranging Time, Enabled by Staircase-Chirp PLL with Sticky-Lock Channel-Switching.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A CMOS Polar Class-G Switched-Capacitor PA With a Single High-Current Supply, for LTE NB-IoT and eMTC.
IEEE J. Solid State Circuits, 2019

2018
A CMOS Polar Single-Supply Class-G SCPA for LTE NB-IoT and Cat-M1.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
A 8mW-RX/113mW-TX, Sub-GHz SoC with time-dithered PA ramping for LPWAN applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 0.9-1.2V supplied, 2.4GHz Bluetooth Low Energy 4.0/4.2 and 802.15.4 transceiver SoC optimized for battery life.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


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