Harish Dattatraya Dixit
Orcid: 0009-0001-1163-5568
According to our database1,
Harish Dattatraya Dixit
authored at least 15 papers
between 2018 and 2025.
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Bibliography
2025
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025
Meta's Second Generation AI Chip: Model-Chip Co-Design and Productionization Experiences.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025
Veritas - Demystifying Silent Data Corruptions: μArch-Level Modeling and Fleet Data of Modern x86 CPUs.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
Hardware Telemetry at Scale: A Case Study on SSDs Endurance Monitoring in Datacenters.
Proceedings of the 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2025
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Hardware Sentinel: Protecting Software Applications from Hardware Silent Data Corruptions.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025
2024
PVF (Parameter Vulnerability Factor): A Quantitative Metric Measuring AI Vulnerability Against Parameter Corruptions.
CoRR, 2024
Proceedings of the IEEE European Test Symposium, 2024
Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale Measurements.
Proceedings of the IEEE European Test Symposium, 2024
2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
2022
Efficient Soft-Error Detection for Low-precision Deep Learning Recommendation Models.
Proceedings of the IEEE International Conference on Big Data, 2022
2021
2020
Optimizing Interrupt Handling Performance for Memory Failures in Large Scale Data Centers.
Proceedings of the ICPE '20: ACM/SPEC International Conference on Performance Engineering, 2020
2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018