We stand with Ukraine

We stand with Ukraine

Hua Xiang

Affiliations:

IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
University of Illinois at Urbana-Champaign, IL, USA (PhD 2004)
University of Texas at Austin, TX, USA (former)

According to our database¹, Hua Xiang authored at least 37 papers between 2001 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2023

Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops.

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Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022

Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.

[BibT_eX]

[DOI]

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Lakshmi N. Reddy

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions.

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Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer.

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[DOI]

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Lakshmi N. Reddy

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Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.

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Lakshmi N. Reddy

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Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Routing-Free Crosstalk Prediction.

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Vishnavi Chauha

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Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Self-Aligned Double-Patterning Aware Legalization.

[BibT_eX]

[DOI]

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Gustavo E. Téllez

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Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2016

Gate movement for timing improvement on row based Dual-VDD designs.

[BibT_eX]

[DOI]

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Lakshmi N. Reddy

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Andrew Sullivan

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Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2014

Row Based Dual-VDD Island Generation and Placement.

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Andrew Sullivan

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Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Network flow based datapath bit slicing.

[BibT_eX]

[DOI]

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Matthew M. Ziegler

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Proceedings of the International Symposium on Physical Design, 2013

Depth controlled symmetric function fanin tree restructure.

[BibT_eX]

[DOI]

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Lakshmi N. Reddy

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Louise Trevillyan

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Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.

[BibT_eX]

[DOI]

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Matthew M. Ziegler

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Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2010

Logical and physical restructuring of fan-in trees.

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[DOI]

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Louise Trevillyan

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Lakshmi N. Reddy

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Proceedings of the 2010 International Symposium on Physical Design, 2010

History-based VLSI legalization using network flow.

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Proceedings of the 47th Design Automation Conference, 2010

2008

Fast Dummy-Fill Density Analysis With Coupling Constraints.

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Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.

[BibT_eX]

[DOI]

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Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Track Routing and Optimization for Yield.

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

OPC-Friendly Bus Driven Floorplanning.

[BibT_eX]

[DOI]

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Martin D. F. Wong

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Dummy fill density analysis with coupling constraints.

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[DOI]

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Martin D. F. Wong

Proceedings of the 2007 International Symposium on Physical Design, 2007

Is your layout density verification exact?: a fast exact algorithm for density calculation.

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Martin D. F. Wong

Proceedings of the 2007 International Symposium on Physical Design, 2007

TROY: Track Router with Yield-driven Wire Planning.

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Proceedings of the 44th Design Automation Conference, 2007

Coupling-aware Dummy Metal Insertion for Lithography.

[BibT_eX]

[DOI]

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Martin D. F. Wong

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Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

An ECO routing algorithm for eliminating coupling-capacitance violations.

[BibT_eX]

[DOI]

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Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Wire density driven global routing for CMP variation and timing.

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Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

An algorithm for integrated pin assignment and buffer planning.

[BibT_eX]

[DOI]

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Martin D. F. Wong

ACM Trans. Design Autom. Electr. Syst., 2005

Wire Planning with Bounded Over-the-Block Wires.

[BibT_eX]

[DOI]

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Martin D. F. Wong

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.

[BibT_eX]

[DOI]

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Martin D. F. Wong

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

New Strategies for High Performance VLSI Physical Design

[BibT_eX]

[DOI]

PhD thesis, 2004

Bus-driven floorplanning.

[BibT_eX]

[DOI]

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Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].

[BibT_eX]

[DOI]

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Martin D. F. Wong

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An ECO algorithm for eliminating crosstalk violations.

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Proceedings of the 2004 International Symposium on Physical Design, 2004

2003

Min-cost flow-based algorithm for simultaneous pin assignment and routing.

[BibT_eX]

[DOI]

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Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Wire type assignment for FPGA routing.

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Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

ECO algorithms for removing overlaps between power rails and signal wires.

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Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.

[BibT_eX]

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Proceedings of the 2002 Design, 2002

2001

An Algorithm for Simultaneous Pin Assignment and Routing.

[BibT_eX]

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Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints.

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Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

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