Hye-Yoon Joo
Orcid: 0000-0001-7126-4589
According to our database1,
Hye-Yoon Joo
authored at least 6 papers
between 2010 and 2022.
Collaborative distances:
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Bibliography
2022
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2016
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010