Jeong-Don Lim
According to our database1,
Jeong-Don Lim authored at least 7 papers
between 2010 and 2022.
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Bibliography
2022
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2020
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010