Timothy Mark Pinkston

According to our database1, Timothy Mark Pinkston authored at least 71 papers between 1991 and 2016.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to design and analysis of interconnection networks and routing algorithms".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors.
IEEE Trans. Computers, 2016

Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator.
J. Parallel Distributed Comput., 2016

2015
Power punch: Towards non-blocking power-gating of NoC routers.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

TAPP: temperature-aware application mapping for NoC-based many-core processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
PAIS: Parallelism-aware interconnect scheduling in multicores.
ACM Trans. Embedded Comput. Syst., 2014

Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Balancing On-Chip Network Latency in Multi-application Mapping for Chip-Multiprocessors.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

MP3: Minimizing performance penalty for power-gating of Clos network-on-chip.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
An Analytical Performance Model for Partitioning Off-Chip Memory Bandwidth.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

RAIR: Interference Reduction in Regionalized Networks-on-Chip.
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

Bubble coloring: avoiding routing- and protocol-induced deadlocks with minimal virtual channel requirement.
Proceedings of the International Conference on Supercomputing, 2013

Worm-Bubble Flow Control.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Communication-Aware Globally-Coordinated On-Chip Networks.
IEEE Trans. Parallel Distrib. Syst., 2012

Efficient implementation of globally-aware network flow control.
J. Parallel Distributed Comput., 2012

NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011
Buses and Crossbars.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Critical Bubble Scheme: An Efficient Implementation of Globally Aware Network Flow Control.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Thread criticality support in on-chip networks.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip.
Proceedings of the 39th International Conference on Parallel Processing, 2010

2008
An Efficient and Deadlock-Free Network Reconfiguration Protocol.
IEEE Trans. Computers, 2008

A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Characterizing the Cell EIB On-Chip Network.
IEEE Micro, 2007

On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

2006
A Design Methodology for Efficient Application-Specific On-Chip Interconnects.
IEEE Trans. Parallel Distrib. Syst., 2006

2005
Distributed Resolution of Network Congestion and Potential Deadlock Using Reservation-Based Scheduling.
IEEE Trans. Parallel Distrib. Syst., 2005

Guest Editorial: Special Section on On-Chip Networks.
IEEE Trans. Parallel Distrib. Syst., 2005

Part II: A Methodology for Developing Deadlock-Free Dynamic Network Reconfiguration Processes.
IEEE Trans. Parallel Distrib. Syst., 2005

Part I: A Theory for Deadlock-Free Dynamic Network Reconfiguration.
IEEE Trans. Parallel Distrib. Syst., 2005

Trends toward on-chip networked microsystems.
IJHPCN, 2005

Performance Analysis of Unstructured Peer-to-Peer Schemes In Integrated Wired and Wireless Network Environments.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

2004
Deadlock-free dynamic reconfiguration over InfiniBandTM NETWORKS.
Parallel Algorithms Appl., 2004

Evaluation of queue designs for true fully adaptive routers.
J. Parallel Distributed Comput., 2004

Simple Deadlock-Free Dynamic Network Reconfiguration.
Proceedings of the High Performance Computing, 2004

2003
A Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems.
IEEE Trans. Parallel Distrib. Syst., 2003

Deadlock-Free Dynamic Reconfiguration Schemes for Increased Network Dependability.
IEEE Trans. Parallel Distrib. Syst., 2003

InfiniBand: The "De Facto" Future Standard for System and Local Area Networks or Just a Scalable Replacement for PCI Buses?
Cluster Computing, 2003

The Performance of Routing Algorithms under Bursty Traffic Loads.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

A Method for Applying Double Scheme Dynamic Reconfiguration over InfiniBandTM.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

A Methodology for Developing Dynamic Network Reconfiguration Processes.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

Evaluation of a Subnet Management Mechanism for InfiniBand Networks.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

Topic Introduction.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

On the InfiniBand Subnet Discovery Process.
Proceedings of the 2003 IEEE International Conference on Cluster Computing (CLUSTER 2003), 2003

2002
Characterization of Deadlocks in Irregular Networks.
J. Parallel Distributed Comput., 2002

A New Mechanism for Congestion and Deadlock Resolution.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

2001
A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources.
IEEE Trans. Parallel Distrib. Syst., 2001

Evaluation of Crossbar Architectures for Deadlock Recovery Routers.
J. Parallel Distributed Comput., 2001

Efficient Handling of Message-Dependent Deadlock.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

2000
A Formal Model of Message Blocking and Deadlock Resolution in Interconnection Networks.
IEEE Trans. Parallel Distrib. Syst., 2000

A New Token-Based Channel Access Protocol for Wavelength Division Multiplexed Multiprocessor Interconnects.
J. Parallel Distributed Comput., 2000

The Double Scheme: Deadlock-Free Dynamic Reconfiguration of Cut-Through Networks.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

On Message.Dependent Deadlocks in Multiprocessor/Multicomputer Systems.
Proceedings of the High Performance Computing, 2000

1999
Characterization of Deadlocks in k-ary n-Cube Networks.
IEEE Trans. Parallel Distrib. Syst., 1999

Flexible and Efficient Routing Based on Progressive Deadlock Recovery.
IEEE Trans. Computers, 1999

1998
Modeling Free-Space Optical k-ary n-Cube Wormhole Networks.
J. Parallel Distributed Comput., 1998

Computer engineering using innovative instructional technologies at the University of Southern California.
Proceedings of the 1998 workshop on Computer architecture education, 1998

A clustering approach in characterizing interconnection networks.
Proceedings of the 5th International Conference On High Performance Computing, 1998

1997
SPEED DMON: Cache Coherence on an Optical Multichannel Interconnect Architecture.
J. Parallel Distributed Comput., 1997

Modeling Message Blocking and Deadlock in Interconnection Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997

On Deadlocks in Interconnection Networks.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Characterization of Deadlocks in Interconnection Networks.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Crossbar Analysis for Optimal Deadlock Recovery Router Architecture.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Software-Based Deadlock Recovery Technique for True Fully Adaptive Routing in Wormhole Networks.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
Generalized Theory for Deadlock-Free Adaptive Wormhole Routing and its Application to Disha Concurrent.
Proceedings of IPPS '96, 1996

An Optical Interconnect Model for k-ary n-cube Wormhole Networks.
Proceedings of IPPS '96, 1996

A Hybrid cache Coherence Protocol for a Decoupled Multi-Channel Optical Network: SPEED DMON.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

1995
Applying Optical Interconnects to the 3-D Computer: A Performance Evaluation.
J. Parallel Distributed Comput., 1995

An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

DISHA: a deadlock recovery scheme for fully adaptive routing.
Proceedings of IPPS '95, 1995

1991
Parallel Processor Memory Reference Analysis: Examining Locality and Clustering Potential.
Proceedings of the Fifth SIAM Conference on Parallel Processing for Scientific Computing, 1991


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