Jitendra Bhandari

Orcid: 0000-0003-1017-1690

According to our database1, Jitendra Bhandari authored at least 24 papers between 2021 and 2025.

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Bibliography

2025
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction.
ACM Trans. Design Autom. Electr. Syst., July, 2025

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code.
CoRR, June, 2025

SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design.
CoRR, June, 2025

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction.
CoRR, June, 2025

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination.
CoRR, March, 2025

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding.
CoRR, March, 2025

DEFending Integrated Circuit Layouts.
IEEE Trans. Inf. Forensics Secur., 2025

LiCSPA: Lightweight Countermeasure against Static Power Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI.
CoRR, 2024

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions.
CoRR, 2024

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search.
CoRR, 2024

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines.
CoRR, 2024

Lightweight Masking Against Static Power Side-Channel Attacks.
CoRR, 2024

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

DEFending Integrated Circuit Layouts.
IACR Cryptol. ePrint Arch., 2023

ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

2022
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

ALICE: an automatic design flow for eFPGA redaction.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Security Closure of Physical Layouts ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploring eFPGA-based Redaction for IP Protection.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021


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