Johannes Geier

Orcid: 0000-0002-9439-3890

According to our database1, Johannes Geier authored at least 12 papers between 2021 and 2026.

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Bibliography

2026

Multi-Partner Project: Advancing European Semiconductor and Chiplet Innovation Through the Bavarian Chip Design Center.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

Quantifying Compiler-induced Reliability Loss in Software-Implemented Hardware Fault Tolerance.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Automated Graph-level Passes for TinyML Fault Tolerance.
Proceedings of the International Joint Conference on Neural Networks, 2025

Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks.
Proceedings of the Design, Automation & Test in Europe Conference, 2025


Towards a Metric to Assess Neural Network Resilience Against Adversarial Samples.
Proceedings of the Availability, Reliability and Security, 2025

2024
XCP<sup>2</sup>: An XCP-Proxy Server for Concurrent Multinode XCP Access.
Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024

2023
vRTLmod: An LLVM based Open-source Tool to Enable Fault Injection in Verilator RTL Simulations.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Key-Recovery Fault Injection Attack on the Classic McEliece KEM.
Proceedings of the Code-Based Cryptography - 10th International Workshop, 2022

2021
Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021


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