Kaveh Shamsi

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

TIPLock: Key-Compressed Logic Locking using Through-Input-Programmable Lookup-Tables.

[BibT_eX]

[DOI]

Rajesh Kumar Datta

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Reevaluating Graph-Neural-Network-Based Runtime Prediction of SAT-Based Circuit Deobfuscation.

[BibT_eX]

[DOI]

Cryptogr., 2022

A Security Analysis of Circuit Clock Obfuscation.

[BibT_eX]

[DOI]

Cryptogr., 2022

Graph Neural Network based Netlist Operator Detection under Circuit Rewriting.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Oracle-Less Machine-Learning Attack against Lookup-Table-based Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

In Praise of Exact-Functional-Secrecy in Circuit Locking.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

Circuit Deobfuscation from Power Side-Channels using Pseudo-Boolean SAT.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2019

IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2019

On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits.

[BibT_eX]

[DOI]

David Z. Pan

Proceedings of the International Conference on Computer-Aided Design, 2019

On the Impossibility of Approximation-Resilient Circuit Locking.

[BibT_eX]

[DOI]

David Z. Pan

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

The Old Frontier of Reverse Engineering: Netlist Partitioning.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2018

TimingSAT: Decamouflaging Timing-based Logic Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

R2D2: Runtime reassurance and detection of A2 Trojan.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

AppSAT: Approximately deobfuscating integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Emerging Technology-Based Design of Primitives for Hardware Security.

[BibT_eX]

[DOI]

Yu Bi

Pierre-Emmanuel Gaillardon

Jiann-Shiun Yuan

ACM J. Emerg. Technol. Comput. Syst., 2016

Security of emerging non-volatile memories: Attacks and defenses.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Hardware Security Challenges Beyond CMOS: Attacks and Remedies.

[BibT_eX]

[DOI]

Wujie Wen

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Voting system design pitfalls: Vulnerability analysis and exploitation of a model platform.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Provably secure camouflaging strategy for IC protection.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Enhancing Hardware Security with Emerging Transistor Technologies.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Leverage Emerging Technologies For DPA-Resilient Block Cipher Design.

[BibT_eX]

[DOI]

Yu Bi

François-Xavier Standaert

Jiann-Shiun Yuan

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.

[BibT_eX]

[DOI]

Yu Bi