Liang Qi

Orcid: 0000-0002-9512-4529

Affiliations:

Shanghai Jiao Tong University, Shanghai, China
University of Macau, Macau, China (PhD)

According to our database¹, Liang Qi authored at least 59 papers between 2017 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2025

A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, May, 2025

A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 2025

A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

An Energy-Efficient FD-fNIRS Readout Circuit Employing a Mixer-First Analog Frontend and a $\Sigma$-$\Delta$ Phase-to-Digital Converter.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., August, 2024

A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A TFT-Based Flexible PPG Acquisition Circuit in a 3-μm LTPS Process for Packaging-Free Smart Ring Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Re-Configurable Body Channel Transceiver Towards Wearable and Flexible Biomedical Sensor Networks.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., October, 2023

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 2023

A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

A Zoom Architecture Using Linear-Exponential Incremental ADC.

[BibT_eX]

[DOI]

Qingxun Wang

Kaiquan Chen

Liang Qi

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Two-step Linear-Exponential Incremental ADC with Slope Extended Counting.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Weightings in Incremental ADCs: A Tutorial Review.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A CT DSM with DAC Scaling Technique for Direct Neural Recording Front-End.

[BibT_eX]

[DOI]

Yuekai Liu

Jinlei Pan

Liang Qi

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Low-Noise, High-Linearity Sine-Wave Generation Using Noise-Shaping Phase-Switching Technique.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2022

Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A VCO-Based CTDSM With Integrated Phase Error Correction for Neural Interface.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Hybrid 1st/2nd-Order VCO-Based CTDSM With Rail-to-Rail Artifact Tolerance for Bidirectional Neural Interface.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 124 dB dynamic range sigma-delta modulator applied to non-invasive EEG acquisition using chopper-modulated input-scaling-down technique.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2022

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Sub-0.01° Phase Resolution 6.8-mW fNIRS Readout Circuit Employing a Mixer-First Frequency-Domain Architecture.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

A power-efficient and re-configurable analog artificial neural network classifier.

[BibT_eX]

[DOI]

Ahmed Reda Mohamed

Liang Qi

Guoxing Wang

Microelectron. J., 2021

A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

An Ultra-Low-Voltage Level Shifter With Embedded Re-Configurable Logic and Time-Borrowing Latch Technique.

[BibT_eX]

[DOI]

IEEE Access, 2021

Self-coupled MASH Delta-Sigma Modulator with Zero Optimization.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Continuous-time Delta-Sigma Modulators: Single-loop versus MASH.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Multi-Rate Hybrid DT/CT Mash ΔΣ Modulator with High Tolerance to Noise Leakage.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Discrete-Time MASH Delta-Sigma Modulator with an IIR-based Self-Coupling.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 10-Mbps 119.2-pJ/bit Software Defined Body Channel Transceiver Employing a CCII-based PGA and a 2.5-bit/cycle ADC in 180-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

An Adaptively-controlled High-efficiency Buck Converter with Wide Dynamic Range for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Low-Hardware-Cost SNN employing FeFET-based Neurons with Tunable Leaky Effect.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

Advances in Continuous-time MASH ΔΣ Modulators.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A Generic Nano-Watt Power Fully Tunable 1-D Gaussian Kernel Circuit for Artificial Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Self-coupled DT MASH ΔΣ Modulator with High Tolerance to Noise Leakage.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications.

[BibT_eX]

[DOI]

Liang Qi

Sai-Weng Sin

Rui Paulo Martins

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Liang Qi

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