Lukasz G. Szafaryn

According to our database1, Lukasz G. Szafaryn authored at least 8 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2016
Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
The resilience wall: Cross-layer solution strategies.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core.
IEEE Micro, 2013

Trellis: Portability across architectures with a high-level framework.
J. Parallel Distributed Comput., 2013

2010
A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010


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