Marco Pasotti
Orcid: 0000-0003-4988-9982
  According to our database1,
  Marco Pasotti
  authored at least 36 papers
  between 1999 and 2024.
  
  
Collaborative distances:
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Bibliography
  2024
Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
    
  
Drift-Tolerant Implementation of a Neural Network on a PCM-Based Analog In-Memory Computing Unit for Motor Control Applications.
    
  
    Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
    
  
Impact of Input Encoding and ADC Resolution on Matrix-Vector Multiplication Accuracy.
    
  
    Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
    
  
A Bit-Line Biasing Circuit for Analog In-Memory Computing Based on Phase Change Memory.
    
  
    Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
    
  
    Proceedings of the IEEE International Reliability Physics Symposium, 2024
    
  
  2023
Combined HW/SW Drift and Variability Mitigation for PCM-Based Analog In-Memory Computing for Neural Network Applications.
    
  
    IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
    
  
  2022
    J. Comput. Civ. Eng., 2022
    
  
Phase-change memory cells characterization in an analog in-memory computing perspective.
    
  
    Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
    
  
    Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
    
  
An embedded PCM Peripheral Unit adding Analog MAC In-Memory Computing Feature addressing Non-linearity and Time Drift Compensation.
    
  
    Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
    
  
  2021
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
    
  
  2020
    Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
    
  
Enhanced Compensation for Voltage Regulators Based on Three-Stage CMOS Operational Amplifiers for Large Capacitive Loads.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
    
  
  2019
Current Tracking Technique Enabling 1-Bit/Cell Storage in Ge-Rich Phase Change Memory.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2019
    
  
    Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
    
  
Drift induced rigid current shift in Ge-Rich GST Phase Change Memories in Low Resistance State.
    
  
    Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
    
  
2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications.
    
  
    Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
    
  
  2018
    Microelectron. J., 2018
    
  
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications.
    
  
    IEEE J. Solid State Circuits, 2018
    
  
  2017
Single charge-pump generating high positive and negative voltages driving common load.
    
  
    Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
    
  
A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications.
    
  
    Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
    
  
  2016
Enhanced voltage buffer compensation technique for two-stage CMOS operational amplifiers.
    
  
    Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
    
  
  2011
A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology.
    
  
    IEEE J. Solid State Circuits, 2011
    
  
  2010
A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2010
    
  
  2008
Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications.
    
  
    Proceedings of the ESSCIRC 2008, 2008
    
  
  2006
    Microelectron. J., 2006
    
  
  2005
How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.
    
  
    Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
    
  
    Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
    
  
    Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
    
  
A 1 V, 26 μW extended temperature range band-gap reference in 130-nm CMOS technology.
    
  
    Proceedings of the 31st European Solid-State Circuits Conference, 2005
    
  
  2003
    IEEE J. Solid State Circuits, 2003
    
  
    Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
    
  
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.
    
  
    Proceedings of the 40th Design Automation Conference, 2003
    
  
  1999
    Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999