Na Bai

According to our database, Na Bai authored at least 32 papers between 2012 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications.

Aibin Yan, Jiajia Zhang, Xiumin Xu, Hanxiang Li, Na Bai, Zhengfeng Huang, Xiaolei Wang, Xiaoqing Wen, Patrick Girard

IEEE Trans. Very Large Scale Integr. Syst., October, 2025

A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments.

Na Bai, Yusheng Xia, Yaohua Xu, Yi Wang, Shaowei Wang, Xiaoqing Wen

IEEE Trans. Very Large Scale Integr. Syst., September, 2025

Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments.

Na Bai, Fudong Wang, Yaohua Xu, Shaowei Wang, Xiaoqing Wen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025

Triple-Node-Upset Recovery High-Impedance-State-Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications.

Aibin Yan, Zhuoyuan Lin, Yongkang Xu, Na Bai, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen

IEEE Trans. Aerosp. Electron. Syst., August, 2025

Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS.

Aibin Yan, Yongkang Xu, Yue Zhang, Na Bai, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement.

Aibin Yan, Changli Hu, Jing Li, Na Bai, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen

IEEE Trans. Very Large Scale Integr. Syst., June, 2025

Low-iteration hybrid computing CORDIC architecture.

Na Bai, Ruizheng Qu, Yaohua Xu, Yi Wang, Xiaojie Chen, Li Li

Microelectron. J., 2025

An enhanced interlocked feedback structure-based dual-node upset resilient latch.

Na Bai, Zhiwei Liu, Xiaoqing Wen, Yaohua Xu, Yi Wang, Jian Chen, Wenhao Zhu

Microelectron. J., 2025

Multi-Task Graph Attention Net for Electricity Consumption Prediction and Anomaly Detection.

Na Bai, Jian Zhang, Zhaoli Wu

Comput., 2025

Abuttable Analog Cell Library and Automatic AMS Layout.

Tianjia Zhou, Cheng Chang, Li Huang, Jingyun Gu, Zexin Ji, Xiangyang Liu, Hailang Liang, Zhanfei Chen, Ting-Jung Lin, Song Wang, Na Bai, Zhengping Li, Lei He

Proceedings of the 2025 International Symposium on Physical Design, 2025

APCer: An Agile Physical Compiler for Multi-Port Register File.

Na Bai, Tianbo Ming, Biwei Liu, Yaohua Xu, Yi Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

A 14T radiation hardened SRAM for space applications with high reliability.

Na Bai, Zhangyi Qin, Li Li, Yaohua Xu, Yi Wang

Int. J. Circuit Theory Appl., June, 2024

Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications.

Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection.

Na Bai, Xiangyang Liu, Xinjie Zhou, Yaohua Xu, Yi Wang

Integr., 2024

AMSNet: Netlist Dataset for AMS Circuits.

Zhuofu Tao, Yichen Shi, Yiru Huo, Rui Ye, Zonghang Li, Li Huang, Chen Wu, Na Bai, Zhiping Yu, Ting-Jung Lin, Lei He

CoRR, 2024

Deep Learning Methods With the Improved Attention for Explainable Image Recognition.

Na Bai, Inwhee Joe

IEEE Access, 2024

A Low-Energy Critical Charge-Enhanced SRAM for Aerospace Applications.

Na Bai, Weihao Zhao, Yaohua Xu, Yi Wang

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

Design of SEU and DNU-resistant SRAM cells based on polarity reinforcement feature.

Na Bai, Zihan Chen, Yaohua Xu, Yi Wang, Yueliang Zhou, Zeyuan Lin

Int. J. Circuit Theory Appl., October, 2023

A multi-task attention tree neural net for stance classification and rumor veracity detection.

Na Bai, Fanrong Meng, Xiaobin Rui, Zhixiao Wang

Appl. Intell., May, 2023

JUTAR: Joint User-Association, Task-Partition, and Resource-Allocation Algorithm for MEC Networks.

Ling Kang, Yi Wang, Yanjun Hu, Fang Jiang, Na Bai, Yu Deng

Sensors, February, 2023

Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications.

Na Bai, Yueliang Zhou, Yaohua Xu, Yi Wang, Zihan Chen

Integr., 2023

2022

An interpretable deep learning workflow for discovering subvisual abnormalities in CT scans of COVID-19 inpatients and survivors.

Longxi Zhou, Xianglin Meng, Yuxin Huang, Kai Kang, Juexiao Zhou, Yuetan Chu, Haoyang Li, Dexuan Xie, Jiannan Zhang, Weizhen Yang, Na Bai, Yi Zhao, Mingyan Zhao, Guohua Wang, Lawrence Carin, Xigang Xiao, Kaijiang Yu, Zhaowen Qiu, Xin Gao

Nat. Mach. Intell., 2022

Naive Bayes classifier based on memristor nonlinear conductance.

Li Li, Zuopai Zhou, Na Bai, Tao Wang, Kanhao Xue, Huajun Sun, Qiang He, Weiming Cheng, Xiangshui Miao

Microelectron. J., 2022

Rumor detection based on a Source-Replies conversation Tree Convolutional Neural Net.

Na Bai, Fanrong Meng, Xiaobin Rui, Zhixiao Wang

Computing, 2022

Logic Design and Power Optimization of Floating-Point Multipliers.

Na Bai, Hang Li, Jiming Lv, Shuai Yang, Yaohua Xu

Comput. Intell. Neurosci., 2022

2021

A Design of a Developable Automatic Avoidance System of UAV Based on ADS-B.

Xuzheng Zhang, Yifei Meng, Chenxiao Mao, Yaohua Xu, Na Bai

Wirel. Commun. Mob. Comput., 2021

Rumour Detection Based on Graph Convolutional Neural Net.

Na Bai, Fanrong Meng, Xiaobin Rui, Zhixiao Wang

IEEE Access, 2021

2020

A Stochastic Attention CNN Model for Rumor Stance Classification.

Na Bai, Zhixiao Wang, Fanrong Meng

IEEE Access, 2020

2014

A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers.

Jianhui Wu, Jiafeng Zhu, YingCheng Xia, Na Bai

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Built-in self test design of power switch with clock-gated charge/discharge transistor.

Xin Chen, Ning Wu, Na Bai, Hui Huang, Wei Hu

IET Comput. Digit. Tech., 2014

2013

A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit.

Jiafeng Zhu, Na Bai, Jianhui Wu

Microelectron. J., 2013

2012

Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design.

Ruixing Lu, Na Bai, Baitao Lv, Jiafeng Zhu, Xiulong Wu

Proceedings of the Seventh IEEE International Conference on Networking, 2012