Christian Bernard
According to our database1,
Christian Bernard
authored at least 20 papers
between 2007 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Proceedings of the 29th Americas Conference on Information Systems, 2023
2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021
2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2018
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectron. J., 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007