Ryuichi Sakamoto

Orcid: 0000-0002-2999-100X

According to our database1, Ryuichi Sakamoto authored at least 30 papers between 2012 and 2023.

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Bibliography

2023
An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications.
Microprocess. Microsystems, 2023

Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems.
Int. J. Netw. Comput., 2023

Extendable MQTT Broker for Feedback-based Resource Management in Large-scale Computing Environments.
Proceedings of the 7th Asia-Pacific Workshop on Networking, 2023

2022
GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022

Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Hash Distributed A* on an FPGA.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

2021
Lexicographic and reverse lexicographic quadratic Gröbner bases of cut ideals.
J. Symb. Comput., 2021

Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems.
IEICE Trans. Electron., 2021

Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

Dynamic Power Management for 5G Small Cell Base Station.
Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021

2020
Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine.
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020

The Effectiveness of Low-Precision Floating Arithmetic on Numerical Codes: A Case Study on Power Consumption.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

2019
Generation High resolution 3D model from natural language by Generative Adversarial Network.
CoRR, 2019

A Preliminary Evaluation of Building Block Computing Systems.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

2018
OpenCL Runtime for OS-Driven Task Pipelining on Heterogeneous Accelerators.
Proceedings of the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2018

Analyzing Resource Trade-offs in Hardware Overprovisioned Supercomputers.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

2017
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Scalable deep neural network accelerator cores with cubic integration using through chip interface.
Proceedings of the International SoC Design Conference, 2017

Production Hardware Overprovisioning: Real-World Performance Optimization Using an Extensible Power-Aware Resource Management Framework.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.
IEICE Trans. Electron., 2016

2015
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.
IEICE Trans. Electron., 2015

2014
Design and evaluation of fine-grained power-gating for embedded microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
IEEE Micro, 2013

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
An OpenCL Runtime Library for Embedded Multi-Core Accelerator.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

A design of hybrid operating system for a parallel computer with multi-core and many-core processors.
Proceedings of the 2nd International Workshop on Runtime and Operating Systems for Supercomputers, 2012

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012


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