According to our database1, Jeremy Constantin authored at least 17 papers between 2012 and 2019.
Legend:Book In proceedings Article PhD thesis Other
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems.
J. Signal Process. Syst., 2017
IEEE Micro, 2017
A low-power correlator for wakeup receivers with algorithm pruning through early termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Statistical fault injection for impact-evaluation of timing errors on application performance.
Proceedings of the 53rd Annual Design Automation Conference, 2016
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms.
Proceedings of the Design, Automation and Test in Europe, 2013
IET Circuits Devices Syst., 2012
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture.
IACR Cryptol. ePrint Arch., 2012
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Multi-core architecture design for ultra-low-power wearable health monitoring systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012