Vanderlei Bonato

According to our database1, Vanderlei Bonato authored at least 35 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Scaling Up Modulo Scheduling for High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE.
Proceedings of the International Conference on Field-Programmable Technology, 2019

ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA.
Signal Processing Systems, 2018

Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Mapping Estimator for OpenCL Heterogeneous Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
Special issue on applied reconfigurable computing.
Microprocess. Microsystems, 2017

Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion.
Appl. Soft Comput., 2016

2015
Application-oriented cache memory configuration for energy efficiency in multi-cores.
IET Computers & Digital Techniques, 2015

Run-time Cache Configuration for the LEON-3 Embedded Processor.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Parameterizable Ethernet Network-on-Chip Architecture on FPGA.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Practical Education Fostered by Research Projects in an Embedded Systems Course.
Int. J. Reconfig. Comp., 2014

A Parallel Hardware Architecture based on Node-Depth Encoding to Solve Network Design Problems.
IJNCR, 2014

Representation of Evolutionary Algorithms in FPGA Cluster for Project of Large-Scale Networks.
CoRR, 2014

2013
A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm.
Signal Processing Systems, 2013

A method to convert floating to fixed-point EKF-SLAM for embedded robotics.
J. Braz. Comp. Soc., 2013

2012
Designing embedded systems with MARTE: A PIM to PSM converter.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012

Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Designing FPGA-based embedded systems with MARTE: A PIM to PSM converter.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

A tool to support Bluespec SystemVerilog coding based on UML diagrams.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

Power/performance optimization in FPGA-based asymmetric multi-core systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2009
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots.
Signal Processing Systems, 2009

RoboArch: A component-based tool proposal for developing hardware architecture for mobile robots.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

2008
Proposal of an FPGA hardware architecture for SLAM using multi-cameras and applied to mobile robotics (Proposta de uma arquitetura de hardware em FPGA implementada para SLAM com multi-câmeras aplicada à robótica móvel).
PhD thesis, 2008

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection.
IEEE Trans. Circuits Syst. Video Techn., 2008

A Parallel Hardware Architecture for Image Feature Detection.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2006
An Embedded Multi-camera System for Simultaneous Localization and Mapping.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2004
Teaching embedded systems with FPGAs throughout a computer science course.
Proceedings of the 2004 workshop on Computer architecture education, 2004

A Real Time Gesture Recognition System for Mobile Robots.
Proceedings of the ICINCO 2004, 2004

2003
Propose of a Hardware Implementation for Fingerprint Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Design of a fingerprint system using a hardware/software environment.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003


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