P. Perreau

According to our database1, P. Perreau authored at least 5 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2014
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2012
Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2010
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009


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