Himanshu Kaul

According to our database1, Himanshu Kaul authored at least 80 papers between 2001 and 2021.

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Bibliography

2021
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS.
IEEE J. Solid State Circuits, 2021

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021

2020
A 4900- $\mu$ m<sup>2</sup> 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition.
IEEE J. Solid State Circuits, 2020

A 0.26% BER, 10<sup>28</sup> Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS.
IEEE J. Solid State Circuits, 2019

A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 4900×m<sup>2</sup> 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018
MetaXplorer: an intelligent and adaptable metasearch engine using a novel ordered weighted averaging operator.
Int. J. Syst. Assur. Eng. Manag., 2018

220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2<sup>4</sup>)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.
IEEE J. Solid State Circuits, 2017

2016
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS.
IEEE J. Solid State Circuits, 2016

250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 350mV-900mV 2.1GHz 0.011mm<sup>2</sup> regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015

Investigating biocomplexity through the agent-based paradigm.
Briefings Bioinform., 2015

μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2<sup>4</sup>)<sup>2</sup> polynomials in 22nm tri-gate CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS.
Proceedings of the ESSCIRC 2014, 2014

2013
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS.
IEEE J. Solid State Circuits, 2013

A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2013

2012
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors.
IEEE J. Solid State Circuits, 2012

A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Near-threshold voltage (NTV) design: opportunities and challenges.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2011

53 Gbps Native GF(2 <sup>4</sup>) <sup>2</sup> Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors.
IEEE J. Solid State Circuits, 2011

A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A robust alternate repeater technique for high performance busses in the multi-core era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS.
Proceedings of the ESSCIRC 2008, 2008

2006
A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2005
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.
IEEE Trans. Very Large Scale Integr. Syst., 2005

High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Power-aware global signaling strategies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel buffer circuit for energy efficient signaling in dual-VDD systems.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

DVS for On-Chip Bus Designs Based on Timing Error Correction.
Proceedings of the 2005 Design, 2005

2004
Low-power on-chip communication based on transition-aware global signaling (TAGS).
IEEE Trans. Very Large Scale Integr. Syst., 2004

Performance optimization of critical nets through active shielding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2002
Active shielding of RLC global interconnects.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Transition Aware Global Signaling (TAGS).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Active shields: a new approach to shielding global wires.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
Power-Driven Challenges in Nanometer Design.
IEEE Des. Test Comput., 2001

Future Performance Challenges in Nanometer Design.
Proceedings of the 38th Design Automation Conference, 2001


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