Jan Madsen

Affiliations:
  • Technical University of Denmark


According to our database1, Jan Madsen authored at least 108 papers between 1989 and 2023.

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Bibliography

2023
Computer Engineering Education.
Computer, November, 2023

Data Aware Neural Architecture Search.
CoRR, 2023

AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
A Primer for tinyML Predictive Maintenance: Input and Model Optimisation.
Proceedings of the Artificial Intelligence Applications and Innovations, 2022

2019
Model-based systems engineering for life-sciences instrumentation development.
Syst. Eng., 2019

Design-for-Testability of On-Chip Control in mVLSI Biochips.
IEEE Des. Test, 2019

2018
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Report on DATE 2018 in Dresden, Germany.
IEEE Des. Test, 2018

2017
D-VASim: an interactive virtual laboratory environment for the simulation and analysis of genetic circuits.
Bioinform., 2017

Test-driven modeling and development of cloud-enabled cyber-physical smart systems.
Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

A systematic and practical method for selecting systems engineering tools.
Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

Co-simulation of cyber physical systems with HMI for human in the loop investigations.
Proceedings of the Symposium on Theory of Modeling & Simulation, Virginia Beach, VA, USA, April 23, 2017

Distributed Co-simulation of Embedded Control Software Using INTO-CPS.
Proceedings of the Simulation and Modeling Methodologies, Technologies and Applications, 2017

Distributed Co-Simulation of Embedded Control Software with Exhaust Gas Recirculation Water Handling System using INTO-CPS.
Proceedings of the 7th International Conference on Simulation and Modeling Methodologies, 2017

Volume management for fault-tolerant continuous-flow microfluidics.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Synthesis of on-chip control circuits for mVLSI biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Logic analysis and verification of n-input genetic logic circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Taming Living Logic Using Formal Methods.
Proceedings of the Models, Algorithms, Logics and Tools, 2017

2016
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Smartphone-based biosensing platform evolution: Implementation of electrochemical analysis capabilities.
Proceedings of the 10th International Symposium on Medical Information and Communication Technology, 2016

Model-Based Evaluation of System Scalability: Bandwidth Analysis for Smartphone-Based Biosensing Applications.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
System-level synthesis of multi-ASIP platforms using an uncertainty model.
Integr., 2015

Redundancy optimization for error recovery in digital microfluidic biochips.
Des. Autom. Embed. Syst., 2015

Test-driven modeling of embedded systems.
Proceedings of the Nordic Circuits and Systems Conference, 2015

A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed for Evolvability.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
EHRA: Specification and Analysis of Energy-Harvesting Wireless Sensor Networks.
Proceedings of the Specification, Algebra, and Software, 2014

Energy Harvesting - Wireless Sensor Networks for Indoors Applications Using IEEE 802.11.
Proceedings of the 5th International Conference on Ambient Systems, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocess. Microsystems, 2013

Module-Based Synthesis of Digital Microfluidic Biochips with Droplet-Aware Operation Execution.
ACM J. Emerg. Technol. Comput. Syst., 2013

Introductions to special issue on ESWEEK 2011.
Des. Autom. Embed. Syst., 2013

Multi-ASIP platform synthesis for real-time applications.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Multi-ASIP platform synthesis for Event-Triggered applications with cost/performance trade-offs.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Hierarchical DSE for multi-ASIP platforms.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Quality-driven model-based design of multi-processor embedded systems for highlydemanding applications.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Control synthesis for the flow-based microfluidic large-scale integration biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Routing-based synthesis of digital microfluidic biochips.
Des. Autom. Embed. Syst., 2012

MDM: A Mode Diagram Modeling Framework
Proceedings of the Proceedings First International Workshop on Formal Techniques for Safety-Critical Systems, 2012

MDM: A Mode Diagram Modeling Framework for Periodic Control Systems
CoRR, 2012

Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

Biochips: The integrated circuit of biology.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Robust and flexible mapping for real-time distributed applications during the early design phases.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Architectural synthesis of flow-based microfluidic large-scale integration biochips.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Expressing Coarse-Grain Dependencies Among Tasks in Shared Memory Programs.
IEEE Trans. Ind. Informatics, 2011

Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

System-level modeling and synthesis of flow-based microfluidic biochips.
Proceedings of the 14th International Conference on Compilers, 2011

Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Application-aware optimization of redundant resources for the reconfigurable self-healing eDNA hardware architecture.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Integration of the self-healing eDNA architecture in a liquid crystal waveguide-based Fourier Transform Spectrometer.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Generating Process Network Communication Infrastructure for Custom Multi-Core Platforms.
Int. J. Embed. Real Time Commun. Syst., 2010

Tabu search-based synthesis of digital microfluidic biochips with dynamically reconfigurable non-rectangular devices.
Des. Autom. Embed. Syst., 2010

DEHAR: A distributed energy harvesting aware routing algorithm for ad-hoc multi-hop wireless sensor networks.
Proceedings of the 11th IEEE International Symposium on a World of Wireless, 2010

Task Mapping and Bandwidth Reservation for Mixed Hard/Soft Fault-Tolerant Embedded Systems.
Proceedings of the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, 2010

Feasibility Study of a Self-healing Hardware Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Task migration for fault-tolerance in mixed-criticality embedded systems.
SIGBED Rev., 2009

Exploration of a digital audio processing platform using a compositional system level performance estimation framework.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

Identifying Inter-task Communication in Shared Memory Programming Models.
Proceedings of the Evolving OpenMP in an Age of Extreme Parallelism, 2009

A compositional modelling framework for exploring MPSoC systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips.
Proceedings of the 2009 International Conference on Compilers, 2009

eDNA: A Bio-Inspired Reconfigurable Hardware Cell Architecture Supporting Self-organisation and Self-healing.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
A Reactive and Cycle-True IP Emulator for MPSoC Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Models and formal verification of multiprocessor system-on-chips.
J. Log. Algebraic Methods Program., 2008

A service based estimation method for MPSoC performance modelling.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable Architectures.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007
ARTS: A SystemC-based framework for multiprocessor Systems-on-Chip modelling.
Des. Autom. Embed. Syst., 2007

COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Semantics and Verification of a Language for Modelling Hardware Architectures.
Proceedings of the Formal Methods and Hybrid Real-Time Systems, 2007

MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Multi-Objective Design Space Exploration of Embedded System Platforms.
Proceedings of the From Model-Driven Design to Resource Management for Distributed Embedded Systems, 2006

2005
A Traffic Injection Methodology with Support for System-Level Synchronization.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

The SoC-Mobinet Model in System-on-Chip Education.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality.
Proceedings of the 13th International Symposium on Modeling, 2005

System-level Modeling of Wireless Integrated Sensor Networks.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

A Network Traffic Generator Model for Fast Network-on-Chip Simulation.
Proceedings of the 2005 Design, 2005

2004
A system-level multiprocessor system-on-chip modeling framework.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

SoC-Mobinet, R&D and education in system-on-chip design.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
Network-on-Chip Modeling for System-Level Multiprocessor Simulation.
Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 2003

Abstract RTOS modeling for multiprocessor system-on-chip.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Power Constrained High-Level Synthesis of Battery Powered Digital Systems.
Proceedings of the 2003 Design, 2003

2002
A Sophomore Course in Codesign.
Computer, 2002

2000
Embedded systems education for the future.
Proc. IEEE, 2000

VRML visualization in a surgery planning and diagnostics application.
Proceedings of the Fifth Symposium on Virtual Reality Modeling Language, 2000

Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Integrating communication protocol selection with hardware/software codesign.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Embedded system synthesis under memory constraints.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Graph based communication analysis for hardware/software codesign.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign.
Proceedings of the 11th International Symposium on System Synthesis, 1998

A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software Codesign.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System.
Proceedings of the 1998 Design, 1998

Communication estimation for hardware/software codesign.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
LYCOS: the Lyngby Co-Synthesis System.
Des. Autom. Embed. Syst., 1997

Validation and testing of sC++ applications.
Proceedings of the 1997 Workshop on Engineering of Computer-Based Systems (ECBS '97), 1997

The importance of interfaces: a HW/SW codesign case study.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

Critical path driven cosynthesis for heterogeneous target architectures.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
Codesign analysis of a computer graphics application.
Des. Autom. Embed. Syst., 1996

Aspects of system modelling in Hardware/Software partitioning.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995
An approach to interface synthesis.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

1994
Modeling shared variables in VHDL.
Proceedings of the Proceedings EURO-DAC'94, 1994

A codesign case study in computer graphics.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Performance Aspects of Gate Matrix Layout.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1991
Single-Level Wiring for CMOS Functional Cells.
Proceedings of the VLSI 91, 1991

Delay estimation for CMOS functional cells.
Proceedings of the conference on European design automation, 1991

1989
A new approach to optimal cell synthesis.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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