Yixin Xu

Orcid: 0000-0001-6393-8635

Affiliations:
  • Pennsylvania State University, University Park, PA, USA


According to our database1, Yixin Xu authored at least 19 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2025
A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024
A Module-Level Configuration Methodology for Programmable Camouflaged Logic.
ACM Trans. Design Autom. Electr. Syst., March, 2024

ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Compact Multiplexer Design with Multi-threshold Ferroelectric FETs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Embedding Security into Ferroelectric FET Array via In-Situ Memory Operation.
CoRR, 2023

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.
CoRR, 2023

Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.
CoRR, 2022

ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key.
CoRR, 2022

CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays.
CoRR, 2022

2021
Hardware Functional Obfuscation With Ferroelectric Active Interconnects.
CoRR, 2021

2020
Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020


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