Zhi Li
Orcid: 0009-0000-9649-7338Affiliations:
- Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
According to our database1,
Zhi Li
authored at least 8 papers
between 2023 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2025
A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025
An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025
SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2025
2024
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference.
IEEE J. Solid State Circuits, October, 2023