Zizheng Guo

Orcid: 0000-0002-0724-5356

Affiliations:
  • Peking University, School of Integrated Circuits, Beijing, China


According to our database1, Zizheng Guo authored at least 32 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
GAP-LA: GPU-Accelerated Performance-Driven Layer Assignment.
CoRR, July, 2025

Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

GEM: GPU-Accelerated Emulator-Inspired RTL Simulation.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

PathGen: An Efficient Parallel Critical Path Generation Algorithm.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Fusion of Global Placement and Gate Sizing with Differentiable Optimization.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

An Efficient Task-Parallel Pipeline Programming Framework.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2024

Heterogeneous Static Timing Analysis with Advanced Delay Calculator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A GPU-Accelerated Framework for Path-Based Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++.
CoRR, 2022

A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

GPU-Accelerated Rectilinear Steiner Tree Generation.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A timing engine inspired graph neural network model for pre-routing slack prediction.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Differentiable-timing-driven global placement.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Efficient Critical Paths Search Algorithm using Mergeable Heap.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Ultrafast CPU/GPU Kernels for Density Accumulation in Placement.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
GPU-Accelerated Static Timing Analysis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020


  Loading...