Alejandro Valero
Orcid: 0000-0002-0824-5833Affiliations:
- University of Zaragoza, Spain
According to our database1,
Alejandro Valero
authored at least 32 papers
between 2009 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
IEEE Trans. Computers, August, 2025
2024
Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage.
Microprocess. Microsystems, 2024
Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators.
J. Syst. Archit., 2024
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
2023
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
2022
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators.
J. Syst. Archit., 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
A learning experience toward the understanding of abstraction-level interactions in parallel applications.
J. Parallel Distributed Comput., 2021
RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU.
CoRR, 2021
2020
IEEE Access, 2020
2019
IEEE Trans. Computers, 2019
IEEE Trans. Computers, 2019
Proceedings of the Workshop on Computer Architecture Education, 2019
2018
Proceedings of the Euro-Par 2018: Parallel Processing, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017
2016
2015
Microprocess. Microsystems, 2015
2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
2013
Proceedings of the International Conference on Supercomputing, 2013
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.
IEEE Trans. Computers, 2012
Combining recency of information with selective random and a victim cache in last-level caches.
ACM Trans. Archit. Code Optim., 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009