Antonio Rubio

According to our database1, Antonio Rubio authored at least 95 papers between 1991 and 2019.

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Bibliography

2019
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Wave Computing with Passive Memristive Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator.
IEEE Trans. Neural Netw. Learning Syst., 2018

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies.
IEEE Trans. Emerging Topics Comput., 2018

Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs.
J. Low Power Electronics, 2018

Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Coupled Physarum-Inspired Memristor Oscillators for Neuron-like Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Memristive Cellular Automata for Modeling of Epileptic Brain Activity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Resistive Switching Behavior seen from the Energy Point of View.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Modem Gain-Cell Memories in Advanced Technologies.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017
Resistive Random Access Memory Variability and Its Mitigation Schemes.
J. Low Power Electronics, 2017

Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.
Proceedings of the 14th International Conference on Synthesis, 2017

Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Exploring the voltage divider approach for accurate memristor state tuning.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Reliability issues in RRAM ternary memories affected by variability and aging mechanisms.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

An on-line test strategy and analysis for a 1T1R crossbar memory.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Multi-modal joint embedding for fashion product retrieval.
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017

Multi-modal Embedding for Main Product Detection in Fashion.
Proceedings of the 2017 IEEE International Conference on Computer Vision Workshops, 2017

Multi-Modal Fashion Product Retrieval.
Proceedings of the Sixth Workshop on Vision and Language, 2017

2016
Feasibility of Embedded DRAM Cells on FinFET Technology.
IEEE Trans. Computers, 2016

Experience on material implication computing with an electromechanical memristor emulator.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016

RRAM variability and its mitigation schemes.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Monitoring SRAM BTI degradation by current-based tracking technique.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A Digital Memristor Emulator for FPGA-Based Artificial Neural Networks.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

BASS: Boundary-Aware Superpixel Segmentation.
Proceedings of the 23rd International Conference on Pattern Recognition, 2016

2015
Adaptive Proactive Reconfiguration: A Technique for Process-Variability- and Aging-Aware SRAM Cache Design.
IEEE Trans. VLSI Syst., 2015

Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections.
Microelectronics Reliability, 2015

Variability Influence on FinFET-Based On-Chip Memory Data Paths.
J. Low Power Electronics, 2015

Special Section on Terascale Computing.
Future Generation Comp. Syst., 2015

Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memories.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Efficient monocular pose estimation for complex 3D models.
Proceedings of the IEEE International Conference on Robotics and Automation, 2015

Memristive crossbar design and test in non-adaptive proactive reconfiguring scheme.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Statistical lifetime analysis of memristive crossbar matrix.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014
A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture.
Microelectronics Reliability, 2014

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET.
Microelectronics Reliability, 2014

Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm.
Microelectronics Journal, 2014

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

INFORMER: An integrated framework for early-stage memory robustness analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Systematic and random variability analysis of two different 6T-SRAM layout topologies.
Microelectronics Journal, 2013

Extending the fundamental error bounds for asymmetric error reliable computation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Reliability study on technology trends beyond 20nm.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Effectiveness of hybrid recovery techniques on parametric failures.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Analysis of FinFET technology on memories.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Shape-shifting digital hardware concept: Towards a new adaptive computing system.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies.
Proceedings of the 2nd European Future Technologies Conference and Exhibition, 2011

New redundant logic design concept for high noise and low voltage scenarios.
Microelectronics Journal, 2011

Design of complex circuits using the Via-Configurable transistor array regular layout fabric.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Analysis of delay mismatching of digital circuits caused by common environmental fluctuations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

New reliability mechanisms in memory design for sub-22nm technologies.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A new probabilistic design methodology of nanoscale digital circuits.
Proceedings of the CONIELECOMP 2011, 21st International Conference on Electrical, Communications, and Computers, 28 February, 2011

Design Guidelines towards Compact Litho-Friendly Regular cells.
Proceedings of the ARCS 2011, 2011

2010
VCTA: A Via-Configurable Transistor Array regular fabric.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

MODEST: a model for energy estimation under spatio-temporal variability.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs.
Microelectronics Journal, 2009

2008
Cell architecture for nanoelectronic design.
Microelectronics Journal, 2008

Data Dependence of Delay Distribution for a Planar Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

The Role of Test in Circuits Built with Unreliable Components.
Proceedings of the 13th European Test Symposium, 2008

Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers.
Proceedings of the 13th European Test Symposium, 2008

2007
Testing in the year 2020.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Dynamic Surface Temperature Measurements in ICs.
Proceedings of the IEEE, 2006

High level spectral-based analysis of power consumption in DSPs systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits.
Microelectronics Journal, 2005

Selective Clock-Gating for Low-Power Synchronous Counters.
J. Low Power Electronics, 2005

Asynchronous pulse logic cell for threshold logic and Boolean networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Applications of temperature phase measurements to IC testing.
Microelectronics Reliability, 2004

Sensing temperature in CMOS circuits for Thermal Testing.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

2002
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs.
IEEE Design & Test of Computers, 2002

2000
Thermal Testing: Fault Location Strategies.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999
Differential Thermal Testing: An Approach to its Feasibility.
J. Electronic Testing, 1999

1997
Differential Sensing Strategy for Dynamic Thermal Testing of ICs.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors.
J. Electronic Testing, 1996

Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Current testability analysis of feedback bridging faults in CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

An approach to dynamic power consumption current testing of CMOS ICs.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Improving Board and System Test: A Proposal to Integrate Boundary Scan and IDDQ.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

A built-in quiescent current monitor for CMOS VLSI circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

An Approach to the Development of a IDDQ Testable Cell Library.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Analysis of the Floating Gate Defect in CMOS.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1991
An approach to the analysis and test of crosstalk faults in digital VLSI circuits.
Proceedings of the conference on European design automation, 1991


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