Hao Wang

Orcid: 0000-0002-7496-633X

Affiliations:
  • Nvidia, Santa Clara, CA, USA
  • Meta, Menlo Park, CA, USA (2019 - 2022)
  • Samsung Austin R&D Center, TX, USA (2015 - 2019)
  • University of Wisconsin-Madison, Madison, WI, USA (PhD 2015)


According to our database1, Hao Wang authored at least 18 papers between 2010 and 2025.

Collaborative distances:

Timeline

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Bibliography

2025
Training Video Foundation Models with NVIDIA NeMo.
CoRR, March, 2025

Cosmos World Foundation Model Platform for Physical AI.
CoRR, January, 2025

2024
Nemotron-4 340B Technical Report.
CoRR, 2024

2023
Workload Behavior Driven Memory Subsystem Design for Hyperscale.
CoRR, 2023

TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
TMO: transparent memory offloading in datacenters.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2019
Ghost routers: energy-efficient asymmetric multicore processors with symmetric NoCs.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

2016
Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors.
IEEE Trans. Parallel Distributed Syst., 2016

DUANG: Fast and lightweight page migration in asymmetric memory systems.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Memory scheduling towards high-throughput cooperative heterogeneous computing.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices.
IEEE Micro, 2013

Improving platform energy: chip area trade-off in near-threshold computing environment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Workload-aware voltage regulator optimization for power efficient multi-core processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Workload and power budget partitioning for single-chip heterogeneous processors.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2010
Temperature dependence of the interface state distribution due to hot carrier effect in FinFET device.
Microelectron. Reliab., 2010

Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010


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