Azeez Bhavnagarwala

According to our database1, Azeez Bhavnagarwala authored at least 11 papers between 1996 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um<sup>2</sup> 6T bitcell in a 16nm FinFET CMOS process.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
Innovative practices session 2C: Advanced in yield learning.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2010
The semiconductor industry in 2025.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing.
IEEE J. Solid State Circuits, 2008

2003
Low-power circuits and technology for wireless digital systems.
IBM J. Res. Dev., 2003

2002
Analysis of the effect of the gate oxide breakdown on SRAM stability.
Microelectron. Reliab., 2002

2001
Interconnect-centric Array Architectures for Minimum SRAM Access Time.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
A minimum total power methodology for projecting limits on CMOS GSI.
IEEE Trans. Very Large Scale Integr. Syst., 2000

CMOS system-on-a-chip voltage scaling beyond 50nm.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1998
Minimum supply voltage for bulk Si CMOS GSI.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1996
Circuit techniques for low-power CMOS GSI.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996


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