Jens Sparsø

According to our database, Jens Sparsø authored at least 82 papers between 1991 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments.

Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms.

Riccardo Miccini, Alessandro Cerioli, Clément Laroche, Tobias Piechowiak, Jens Sparsø, Luca Pezzarossa

CoRR, 2024

2023

Dynamic nsNET2: Efficient Deep Noise Suppression with Early Exiting.

Riccardo Miccini, Alaa Zniber, Clément Laroche, Tobias Piechowiak, Martin Schoeberl, Luca Pezzarossa, Ouassim Karrakchou, Jens Sparsø, Mounir Ghogho

Proceedings of the 33rd IEEE International Workshop on Machine Learning for Signal Processing, 2023

A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks.

Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements.

Kasper Hesse, Tjark Petersen, Jens Sparsø

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022

Comparing timed-division multiplexing and best-effort networks-on-chip.

Jens Sparsø, Hans Jakob Damsgaard, Dimitrios Katsamanis, Martin Schoeberl

J. Syst. Archit., 2022

2021

Synchronizing Real-Time Tasks in Time-Triggered Networks.

Eleftherios Kyriakakis, Jens Sparsø, Peter P. Puschner, Martin Schoeberl

Proceedings of the 24th IEEE International Symposium on Real-Time Distributed Computing, 2021

PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks.

Zuzana Jelcicová, Rasmus Jones, David Thorn Blix, Marian Verhelst, Jens Sparsø

Proceedings of the 29th European Signal Processing Conference, 2021

Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller.

Eleftherios Kyriakakis, Jens Sparsø, Martin Schoeberl

Proceedings of the 26th IEEE International Conference on Emerging Technologies and Factory Automation, 2021

2020

A time-predictable open-source TTEthernet end-system.

Eleftherios Kyriakakis, Maja Lund, Luca Pezzarossa, Jens Sparsø, Martin Schoeberl

J. Syst. Archit., 2020

Synchronizing Real-Time Tasks in Time-Aware Networks: Work-in-Progress.

Eleftherios Kyriakakis, Jens Sparsø, Peter P. Puschner, Martin Schoeberl

Proceedings of the 20th International Conference on Embedded Software, 2020

A Neural Network Engine for Resource Constrained Embedded Systems.

Zuzana Jelcicová, Adrian Mardari, Oskar Andersson, Evangelia Kasapaki, Jens Sparsø

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019

Hardlock: Real-time multicore locking.

Tórur Biskopstø Strøm, Jens Sparsø, Martin Schoeberl

J. Syst. Archit., 2019

S4NOC: a minimalistic network-on-chip for real-time multicores.

Martin Schoeberl, Luca Pezzarossa, Jens Sparsø

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

A Time-predictable TTEthenet Node.

Maja Lund, Luca Pezzarossa, Jens Sparsø, Martin Schoeberl

Proceedings of the IEEE 22nd International Symposium on Real-Time Distributed Computing, 2019

Demonstration of a Time-predictable Flight Controller on a Multicore Processor.

Oktay Baris, Shibarchi Majumder, Tórur Biskopstø Strøm, Anders la Cour-Harbo, Jens Sparsø, Thomas Bak, Martin Schoeberl

Proceedings of the IEEE 22nd International Symposium on Real-Time Distributed Computing, 2019

Implementing time-triggered communication over a standard ethernet switch.

Eleftherios Kyriakakis, Jens Sparsø, Martin Schoeberl

Proceedings of the Workshop on Fog Computing and the IoT, 2019

Scratchpad Memories with Ownership.

Martin Schoeberl, Tórur Biskopstø Strøm, Oktay Baris, Jens Sparsø

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking.

Adrian Mardari, Zuzana Jelcicová, Jens Sparsø

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

A Minimal Network Interface for a Simple Network-on-Chip.

Martin Schoeberl, Luca Pezzarossa, Jens Sparsø

Proceedings of the Architecture of Computing Systems - ARCS 2019, 2019

2018

Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016.

Jens Sparsø

Microprocess. Microsystems, 2018

Using dynamic partial reconfiguration of FPGAs in real-Time systems.

Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø

Microprocess. Microsystems, 2018

A Multicore Processor for Time-Critical Applications.

Martin Schoeberl, Luca Pezzarossa, Jens Sparsø

IEEE Des. Test, 2018

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol.

Eleftherios Kyriakakis, Jens Sparsø, Martin Schoeberl

Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

2017

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip.

Rasmus Bo Sørensen, Luca Pezzarossa, Martin Schoeberl, Jens Sparsø

J. Syst. Archit., 2017

Can real-time systems benefit from dynamic partial reconfiguration?

Luca Pezzarossa, Andreas Toftegaard Kristensen, Martin Schoeberl, Jens Sparsø

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

High-level synthesis for reduction of WCET in real-time systems.

Andreas Toftegaard Kristensen, Luca Pezzarossa, Jens Sparsø

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Timing Organization of a Real-Time Multicore Processor.

Martin Schoeberl, Jens Sparsø

Proceedings of the New Generation of CAS, 2017

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems.

Luca Pezzarossa, Martin Schoeberl, Jens Sparsø

Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

2016

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation.

Evangelia Kasapaki, Martin Schoeberl, Rasmus Bo Sørensen, Christoph Thomas Muller, Kees Goossens, Jens Sparsø

IEEE Trans. Very Large Scale Integr. Syst., 2016

State-based Communication on Time-predictable Multicore Processors.

Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø

Proceedings of the 24th International Conference on Real-Time Networks and Systems, 2016

Reconfiguration in FPGA-based multi-core platforms for hard real-time applications.

Luca Pezzarossa, Martin Schoeberl, Jens Sparsø

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Avionics Applications on a Time-Predictable Chip-Multiprocessor.

André Rocha, Cláudio Silva, Rasmus Bo Sørensen, Jens Sparsø, Martin Schoeberl

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

An area-efficient TDM NoC supporting reconfiguration for mode changes.

Rasmus Bo Sørensen, Luca Pezzarossa, Jens Sparsø

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

2015

T-CREST: Time-predictable multi-core architecture for embedded systems.

Martin Schoeberl, Sahar Abbaspour, Benny Akesson, Neil C. Audsley, Raffaele Capasso, Jamie Garside, Kees Goossens, Sven Goossens, Scott Hansen, Reinhold Heckmann, Stefan Hepp, Benedikt Huber, Alexander Jordan, Evangelia Kasapaki, Jens Knoop, Yonghui Li, Daniel Prokesch, Wolfgang Puffitsch, Peter P. Puschner, André Rocha, Cláudio Silva, Jens Sparsø, Alessandro Tocchi

J. Syst. Archit., 2015

Interfacing hardware accelerators to a time-division multiplexing network-on-chip.

Luca Pezzarossa, Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø

Proceedings of the Nordic Circuits and Systems Conference, 2015

Message Passing on a Time-predictable Multicore Processor.

Rasmus Bo Sørensen, Wolfgang Puffitsch, Martin Schoeberl, Jens Sparsø

Proceedings of the IEEE 18th International Symposium on Real-Time Distributed Computing, 2015

Models of Communication for Multicore Processors.

Martin Schoeberl, Rasmus Bo Sørensen, Jens Sparsø

Proceedings of the 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2015

The Argo NOC: Combining TDM and GALS.

Evangelia Kasapaki, Jens Sparsø

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

A Time-Predictable Memory Network-on-Chip.

Martin Schoeberl, David Vh Chong, Wolfgang Puffitsch, Jens Sparsø

Proceedings of the 14th International Workshop on Worst-Case Execution Time Analysis, 2014

Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools.

Christoph Thomas Muller, Evangelia Kasapaki, Rasmus Bo Sørensen, Jens Sparsø

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Open core protocol (OCP) clock domain crossing interfaces.

Mathias Herlev, Christian Keis Poulsen, Jens Sparsø

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

A loosely synchronizing asynchronous router for TDM-scheduled NOCs.

I. Kotleas, D. Humphreys, Rasmus Bo Sørensen, Evangelia Kasapaki, Florian Brandner, Jens Sparsø

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip.

Rasmus Bo Sørensen, Jens Sparsø, Mark Ruvald Pedersen, Jaspur Hojgaard

Proceedings of the 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014

Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers.

Evangelia Kasapaki, Jens Sparsø

Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013

A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs.

Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip.

Evangelia Kasapaki, Jens Sparsø, Rasmus Bo Sørensen, Kees Goossens

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

An area-efficient network interface for a TDM-based network-on-chip.

Jens Sparsø, Evangelia Kasapaki, Martin Schoeberl

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A light-weight statically scheduled network-on-chip.

Rasmus Bo Sørensen, Martin Schoeberl, Jens Sparsø

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems.

Martin Schoeberl, Florian Brandner, Jens Sparsø, Evangelia Kasapaki

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip.

Jens Sparsø

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2011

The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation.

Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø

ACM Trans. Embed. Comput. Syst., 2011

Analytical derivation of traffic patterns in cache-coherent shared-memory systems.

Matthias Bo Stuart, Jens Sparsø

Microprocess. Microsystems, 2011

Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection.

Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø

IET Comput. Digit. Tech., 2011

2010

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study.

Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø

Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend.

Sune Fallgaard Nielsen, Jens Sparsø, Jan Madsen

IEEE Trans. Very Large Scale Integr. Syst., 2009

Current trends in high-level synthesis of asynchronous circuits.

Jens Sparsø

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip.

Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow.

Sune Fallgaard Nielsen, Jens Sparsø, Jonas Braband Jensen, Johan Sebastian Rosenkilde Nielsen

Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008

A Reactive and Cycle-True IP Emulator for MPSoC Exploration.

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology.

Mikkel Bystrup Stensgaard, Jens Sparsø

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007

A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.

Tobias Bjerregaard, Mikkel Bystrup Stensgaard, Jens Sparsø

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.

Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Packetizing OCP Transactions in the MANGO Network-on-Chip.

Tobias Bjerregaard, Jens Sparsø

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

A Traffic Injection Methodology with Support for System-Level Synchronization.

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip.

Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

A Network Traffic Generator Model for Fast Network-on-Chip Simulation.

Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen

Proceedings of the 2005 Design, 2005

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip.

Tobias Bjerregaard, Jens Sparsø

Proceedings of the 2005 Design, 2005

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip.

Tobias Bjerregaard, Jens Sparsø

Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004

A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing.

Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen

J. VLSI Signal Process., 2004

A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.

Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø

Proceedings of the Integrated Circuit and System Design, 2004

Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation.

Sune Fallgaard Nielsen, Jens Sparsø, Jan Madsen

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2002

Future directions in clocking multi-ghz systems.

Vojin G. Oklobdzija, Jens Sparsø

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1999

Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid.

Lars Skovby Nielsen, Jens Sparsø

Proc. IEEE, 1999

1998

The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core.

Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø

Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1996

A low-power asynchronous data-path for a FIR filter bank.

Lars Skovby Nielsen, Jens Sparsø

Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1994

Low-power operation using self-timed circuits and adaptive scaling of the supply voltage.

Lars Skovby Nielsen, Cees Niessen, Jens Sparsø, Kees van Berkel

IEEE Trans. Very Large Scale Integr. Syst., 1994

1993

Delay-insensitive multi-ring structures.

Jens Sparsø, Jørgen Staunstrup

Integr., 1993

Design of Self-timed Multipliers: A Comparison.

Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup

Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993

1992

Design of delay insensitive circuits using multi-ring structures.

Jens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen

Proceedings of the conference on European design automation, 1992

1991

An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders.

Erik Paaske, Steen Pedersen, Jens Sparsø

Integr., 1991

Design of a Fully Parallel Viterbi Decoder.

Jens Sparsø, Steen Pedersen, Erik Paaske

Proceedings of the VLSI 91, 1991