Jean Durupt

According to our database, Jean Durupt authored at least 13 papers between 1993 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

IEEE J. Solid State Circuits, 2021

2020

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.

Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.

Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2016

IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system.

Jean Durupt, Pascal Vivet, Juergen Schloeffel

Proceedings of the 21th IEEE European Test Symposium, 2016

2009

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.

Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach

IET Comput. Digit. Tech., 2009

2008

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.

Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications.

Carolynn Bernier, Frédéric Hameau, Gérard Billiot, Emeric de Foucauld, Stéphanie Robinet, Didier Lattard, Jean Durupt, Francois Dehmas, Laurent Ouvry, Pierre Vincent

Proceedings of the ESSCIRC 2008, 2008

2007

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.

Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip.

Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A DFT Architecture for Asynchronous Networks-on-Chip.

Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach

Proceedings of the 11th European Test Symposium, 2006

Design-for-Test of Asynchronous Networks-on-Chip.

Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

1993

Experimental multiprocessor architecture dedicated for solving 3D PDEs.

J.-M. Libs, B. Siaud, Jean Durupt, Bernard Boutherin, Gilles Jacquemod, Michel Le Helley

Proceedings of the 1993 Euromicro Workshop on Parallel and Distributed Processing, 1993