Eric Guthmuller

Orcid: 0009-0002-0678-7599

According to our database1, Eric Guthmuller authored at least 14 papers between 2012 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2022
Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor.
Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Trace-driven exploration of sharing set management strategies for cache coherence in manycores.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2015
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

3D advanced integration technology for heterogeneous systems.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

3D stacking for multi-core architectures: From WIDEIO to distributed caches.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

3D integration for power-efficient computing.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Adaptive Stackable 3D Cache Architecture for Manycores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012


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