L. Richard Carley

Orcid: 0000-0003-3945-9110

According to our database1, L. Richard Carley authored at least 101 papers between 1987 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1997, "For contributions to the design o analog integrated circuits and to computer-aided analog design.".

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Beyond Accuracy: Cybersecurity Resilience Evaluation Of Intrusion Detection System Against Dos Attacks Using Agent-Based Simulation.
Proceedings of the Winter Simulation Conference, 2023

Integrating Human Factors into Agent-Based Simulation for Dynamic Phishing Susceptibility.
Proceedings of the Social, Cultural, and Behavioral Modeling, 2023

An Efficient Meta-Reinforcement Learning Approach for Circuit Linearity Calibration via Style Injection.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Improved Change Detection in Longitudinal Social Network Measures Subject to Pattern-of-Life Variations.
Proceedings of the Complex Networks & Their Applications XII, 2023

Modeling and Simulation of the Human Firewall Against Phishing Attacks in Small and Medium-Sized Businesses.
Proceedings of the Annual Modeling and Simulation Conference, 2023

2022
A Deep Reinforcement Learning Framework for High-Dimensional Circuit Linearization.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems.
IEEE J. Solid State Circuits, 2022

Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

OSIRIS: Organization Simulation in Response to Intrusion Strategies.
Proceedings of the Social, Cultural, and Behavioral Modeling, 2022

2021
RACER: Bit-Pipelined Processing Using Resistive Memory.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
4.4 A 28/37GHz Scalable, Reconfigurable Multi-Layer Hybrid/Digital MIMO Transceiver for TDD/FDD and Full-Duplex Communication.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
A Socio-Computational Approach to Predicting Bioweapon Proliferation.
IEEE Trans. Comput. Soc. Syst., 2018

Remote assessment of countries' cyber weapon capabilities.
Soc. Netw. Anal. Min., 2018

Dynamic Network Analytics: Tutorial Outline.
Proceedings of the 24th Annual International Conference on Mobile Computing and Networking, 2018

Chip-to-chip RF Communications and Power Delivery via On-chip Antennas.
Proceedings of the 24th Annual International Conference on Mobile Computing and Networking, 2018

2017
Global Variation in Attack Encounters and Hosting.
Proceedings of the Hot Topics in Science of Security: Symposium and Bootcamp, HoTSoS 2017, 2017

2016
Longitudinal analysis of a large corpus of cyber threat descriptions.
J. Comput. Virol. Hacking Tech., 2016

Technologies for secure RFID authentication of medicinal pills and capsules.
Proceedings of the IEEE International Conference on RFID Technology and Applications, 2016

2015
Remote assessment of countries' nuclear, biological, and cyber capabilities: joint motivation and latent capability approach.
Soc. Netw. Anal. Min., 2015

An empirical study of global malware encounters.
Proceedings of the 2015 Symposium and Bootcamp on the Science of Security, 2015

2014
An incremental algorithm for updating betweenness centrality and k-betweenness centrality and its performance on realistic dynamic social network data.
Soc. Netw. Anal. Min., 2014

2013
Monitoring social centrality for peer-to-peer network protection.
IEEE Commun. Mag., 2013

A 0.7W fully integrated 42GHz power amplifier with 10% PAE in 0.13µm SiGe BiCMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Incremental algorithm for updating betweenness centrality in dynamically growing networks.
Proceedings of the Advances in Social Networks Analysis and Mining 2013, 2013

Incremental closeness centrality for dynamically changing social networks.
Proceedings of the Advances in Social Networks Analysis and Mining 2013, 2013

2012
What if wireless routers were social? approaching wireless mesh networks from a social networks perspective.
IEEE Wirel. Commun., 2012

Trends in science networks: understanding structures and statistics of scientific networks.
Soc. Netw. Anal. Min., 2012

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement.
IEEE J. Solid State Circuits, 2012

Analyzing scientific networks for nuclear capabilities assessment.
J. Assoc. Inf. Sci. Technol., 2012

What if Routers Were Social? Analyzing Wireless Mesh Networks from a Social Networks Perspective
CoRR, 2012

Frequency scaling of power reclamation networks in outphasing PA architectures.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Who was Where, When? Spatiotemporal Analysis of Researcher Mobility in Nuclear Science.
Proceedings of the Workshops Proceedings of the IEEE 28th International Conference on Data Engineering, 2012

2011
A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Electromechanical ΔΣ modulation with high-Q micromechanical accelerometers and pulse density modulated force feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2005
A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Filters and amplifiers.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A 0.5 mm<sup>2</sup> integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A low-noise low-offset capacitive sensing amplifier for a 50-μg√Hz monolithic CMOS MEMS accelerometer.
IEEE J. Solid State Circuits, 2004

A CMOS-MEMS magnetic thin-film inductor for radio frequency and intermediate frequency filter circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.
Proceedings of the 41th Design Automation Conference, 2004

8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3<sup>rd</sup> order, 3/5-bit IIR and 3<sup>rd</sup> order 3-bit-FIR noise shapers in 90nm CMOS.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Analysis of switched-capacitor common-mode feedback circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

2002
Micromachined high-Q inductors in a 0.18-μm copper interconnect low-k dielectric CMOS process.
IEEE J. Solid State Circuits, 2002

Remembrance of circuits past: macromodeling by data mining in large analog design spaces.
Proceedings of the 39th Design Automation Conference, 2002

2001
Low-power technology mapping for mixed-swing logic.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A simulation study of electromechanical delta-sigma modulators.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Mixed-swing methodology for domino logic circuits.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Micromachined high-Q inductors in 0.18 μm Cu interconnect low-K CMOS.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Teaching "Introduction to electrical and computer engineering" in context.
Proc. IEEE, 2000

A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbi detector for disk drive read channels.
IEEE J. Solid State Circuits, 2000

MEMS-based integrated-circuit mass-storage systems.
Commun. ACM, 2000

An adaptive on-chip voltage regulation technique for low-power applications.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC.
Proceedings of the 37th Conference on Design Automation, 2000

A Table-Based Time-Domain Simulation Method for Oversampled Microelectromechanical Systems.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1999
Device-level early floorplanning algorithms for RF circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Mixed-swing quadrail for low power dual-rail domino logic.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Inverse polarity techniques for high-speed/low-power multipliers.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A completey on-chip voltage regulation technique for low power digital circuits.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A low distortion high frequency transconductor structure.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Detection for signal-dependent correlated noise in magnetic recording.
Proceedings of the 1999 IEEE International Conference on Communications: Global Convergence Through Communications, 1999

MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells.
Proceedings of the 36th Conference on Design Automation, 1999

A 110 MHz 350 mW 0.6μ CMOS 16-state generalized-target Viterbi detector for disk drive read channels.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

ANACONDA: robust synthesis of analog circuits via stochastic pattern search.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
High-speed CMOS continuous-time complex graphic equalizer for magnetic recording.
IEEE J. Solid State Circuits, 1998

Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
Exploring the design space of mixed swing quadrail for low-power digital circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1997

A low-power backward equalizer for DFE read-channel applications.
IEEE J. Solid State Circuits, 1997

1996
Synthesis of high-performance analog circuits in ASTRX/OBLX.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Fabrication and performance of mesa interconnect.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization.
IEEE J. Solid State Circuits, March, 1995

An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC.
IEEE J. Solid State Circuits, March, 1995

Substrate-aware mixed-signal macrocell placement in WRIGHT.
IEEE J. Solid State Circuits, March, 1995

Integer programming based topology selection of cell-level analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

High-Speed CMOS Current-Mode Equalizers.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis.
IEEE J. Solid State Circuits, March, 1994

Efficient sequence detection for intersymbol interference channels with run-length constraints.
IEEE Trans. Commun., 1994

Synthesis of manufacturable analog circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Latchup-aware placement and parasitic-bounded routing of custom analog cells.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
System-level routing of mixed-signal ASICs in WREN.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis.
Proceedings of the 29th Design Automation Conference, 1992

1991
A very fast VLSI rangefinder.
Proceedings of the 1991 IEEE International Conference on Robotics and Automation, 1991

Automating Analog Circuit Design using Constrained Optimization Techniques.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1989
OASYS: a framework for analog circuit synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
Analog circuit synthesis and exploration in OASYS.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Current sensing for built-in testing of CMOS circuits.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

CLANS: a high-level synthesis tool for high resolution data converters.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Analog circuit synthesis for performance in OASYS.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Automatic layout of custom analog cells in ANAGRAM.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Presynaptic Neural Information Processing.
Proceedings of the Neural Information Processing Systems, Denver, Colorado, USA, 1987, 1987

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987


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