Marco Indaco

According to our database1, Marco Indaco authored at least 35 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2019
Design and Review of Water Management System Using Ethernet, Wi-Fi 802.11n, Modbus, and Other Communication Standards.
Wirel. Pers. Commun., 2019

2018
Efficient many-core architecture design for cryptanalytic collision search on FPGAs.
J. Inf. Secur. Appl., 2018

2016
Vision-Based Pose Estimation for Robot-Mediated Hand Telerehabilitation.
Sensors, 2016

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
ACM J. Emerg. Technol. Comput. Syst., 2016

2015
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
ACM Trans. Embed. Comput. Syst., 2015

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An Efficient Many-Core Architecture for Elliptic Curve Cryptography Security Assessment.
IACR Cryptol. ePrint Arch., 2015

A Novel Architectural Pattern to Support the Development of Human-Robot Interaction (HRI) Systems Integrating Haptic Interfaces and Gesture Recognition Algorithms.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Power-aware voltage tuning for STT-MRAM reliability.
Proceedings of the 20th IEEE European Test Symposium, 2015

STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

A cloud robotics system for telepresence enabling mobility impaired people to enjoy the whole museum experience.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

ORIENTOMA: A novel platform for autonomous and safe navigation for blind and visually impaired.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

STT MRAM-Based PUFs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Service Oriented Non-Volatile Memories.
PhD thesis, 2014

FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
ACM Trans. Archit. Code Optim., 2014

Integration of STT-MRAM model into CACTI simulator.
Proceedings of the 9th International Design and Test Symposium, 2014

On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial).
Proceedings of the 19th IEEE European Test Symposium, 2014

Evaluation of image deblurring algorithms for real-time applications.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Real-Time Single Camera Hand Gesture Recognition System for Remote Deaf-Blind Communication.
Proceedings of the Augmented and Virtual Reality - First International Conference, 2014

ABLUR: An FPGA-based adaptive deblurring core for real-time applications.
Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, 2014

2013
Design and optimization of adaptable BCH codecs for NAND flash memories.
Microprocess. Microsystems, 2013

Ef<sup>3</sup>S: An evaluation framework for flash-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Increasing the robustness of CUDA Fermi GPU-based systems.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Blurring prediction in monocular SLAM.
Proceedings of the 8th International Design and Test Symposium, 2013

Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A software-based self test of CUDA Fermi GPUs.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
An area-efficient 2-D convolution implementation on FPGA for space applications.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Validation & Verification of an EDA automated synthesis tool.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A unifying formalism to support automated synthesis of SBSTs for embedded caches.
Proceedings of the 9th East-West Design & Test Symposium, 2011

MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Communication interface synthesis from TLM 2.0 to RTL.
Proceedings of the 2010 East-West Design & Test Symposium, 2010


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