Qi Xu
Orcid: 0000-0002-0375-9800
According to our database1,
Qi Xu
authored at least 48 papers
between 2016 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2025
LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay.
ACM Trans. Design Autom. Electr. Syst., May, 2024
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024
AD<sup>2</sup>VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems.
ACM Trans. Design Autom. Electr. Syst., January, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
OTPlace-Vias: A Novel Optimal Transport Based Method for High Density Vias Placement in 3D Circuits.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources.
ACM Trans. Design Autom. Electr. Syst., November, 2023
A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., January, 2023
ACM Trans. Design Autom. Electr. Syst., 2023
IEEE Trans Autom. Sci. Eng., 2023
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM.
CoRR, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips.
ACM Trans. Design Autom. Electr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs.
CoRR, 2022
PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier.
J. Circuits Syst. Comput., 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
ACM Trans. Design Autom. Electr. Syst., 2020
Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.
IEEE Trans. Circuits Syst., 2020
Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Integr., 2020
Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems.
CoRR, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning.
Appl. Soft Comput., 2016