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Zhen Zhuang

Orcid: 0000-0002-2972-8770

According to our database¹, Zhen Zhuang authored at least 35 papers between 2018 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Links

On csauthors.net:

Bibliography

2026

Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System.

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M. D. Arafat Kabir

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ACM Trans. Design Autom. Electr. Syst., May, 2026

Parallel Delay-Driven Layer Assignment Leveraging Hierarchical Task Graph Modeling for Advanced Technology Nodes.

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IEEE Trans. Computers, March, 2026

Event-Triggered Robust State of Charge Estimation for Lithium-Ion Battery With Cloud-Integrated Battery Management System.

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IEEE Trans. Ind. Electron., February, 2026

Multilayer Package Power/Ground Planes Synthesis With Balanced DC IR Drops: A Game-Theoretic Optimization Approach.

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2026

HiePlace: Efficient Hierarchical PCB Placement.

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2026

Cracking the Code of Backdoor Attacks With Confidence Consistency.

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IEEE Trans. Inf. Forensics Secur., 2026

Distributed optimal consensus for stochastic fractional-order multi-agent systems: Frequency distribution model approach.

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Appl. Math. Comput., 2026

ETLA-3D: Equivalent Thin Layer Aggregation based Thermal FEM for Hybrid Bonding F2F 3D ICs.

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Proceedings of the Design, Automation & Test in Europe Conference, 2026

FastRW: An Efficient Random Walk Method for Steady-State Thermal Analysis.

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Proceedings of the Design, Automation & Test in Europe Conference, 2026

DPO-3D: Differentiable Power Delivery Network Optimization via Flexible Modeling for Routability and IR-Drop Tradeoff in Face-to-Face 3D ICs.

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Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

Graph Attention-Based Current Crowding Analysis at TSV Interfaces in 3D Power Delivery Networks.

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Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

Partitioning-free 3D-IC Floorplanning.

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Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging.

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Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2025

Text-to-Image Diffusion Models Cannot Count, and Prompt Refinement Cannot Help.

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CoRR, March, 2025

Neural Algorithmic Reasoning for Hypergraphs with Looped Transformers.

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CoRR, January, 2025

ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs.

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Martin D. F. Wong

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Proceedings of the 2025 International Symposium on Physical Design, 2025

MMPack: Multi-Mask Co-Design for Ultra-Large Wafer-Scale Package Integration.

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Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs.

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Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Conv-Basis: A New Paradigm for Efficient Attention Inference and Gradient Computation in Transformers.

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Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2025, 2025

GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer Sharing.

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Pruek Vanna-Iampikul

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Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Accelerating k-means ++ Algorithm.

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Proceedings of the IEEE International Conference on Big Data, 2025

Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale Integration.

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Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A Robust Multilayer X-Architecture Global Routing System Based on Particle Swarm Optimization.

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IEEE Trans. Syst. Man Cybern. Syst., September, 2024

Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration.

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Alberto L. Sangiovanni-Vincentelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

2023

Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding.

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Martin D. F. Wong

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition.

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Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Multi-Package Co-Design for Chiplet Integration.

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Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TRADER: A Practical Track-Assignment-Based Detailed Router.

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Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification.

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Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT.

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Soft Comput., 2020

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique.

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Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes.

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Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

X-Architecture Steiner Minimal Tree Construction Based on Discrete Differential Evolution.

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Proceedings of the Advances in Natural Computation, Fuzzy Systems and Knowledge Discovery - Proceedings of the 15th International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery (ICNC-FSKD 2019), Kunming, China, July 20-22, 2019, 2019

RDTA: An Efficient Routability-Driven Track Assignment Algorithm.

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Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

A novel particle swarm optimizer with multi-stage transformation and genetic operation for VLSI routing.

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CoRR, 2018

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